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| author | Wolfgang Draxinger <dw@optores.de> | 2019-07-10 18:08:12 +0200 |
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| committer | Wolfgang Draxinger <dw@optores.de> | 2019-07-10 18:08:12 +0200 |
| commit | 3b5724a1ff7e24b9c4096d7620260f7b905312e3 (patch) | |
| tree | c203e7ebf0ca4e20aa6f451104ce81acfe3dff2b /README | |
| download | dwxy2cent-3b5724a1ff7e24b9c4096d7620260f7b905312e3.tar.gz dwxy2cent-3b5724a1ff7e24b9c4096d7620260f7b905312e3.tar.bz2 | |
Diffstat (limited to 'README')
| -rw-r--r-- | README | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -0,0 +1 @@ +Verilog modules for generating XY2-100 compliant serial signals |