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lar can accept multiple sizes as well (wlx), like lsl. When using
autosize it's important to look at the destination operand first;
when it's a register that one determines the size, not the input
operand.
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Those two insn types are nicer to handle as operand types, because
the pressure for bits on instr_type is higher than for operands.
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Now we can express prefixes with 0x0fxx opcodes we can correct the
movq mem64->xmm opcode, and restrict the movq xmm->mem64 movq to
not invalidly accept mmx.
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Now that we can store prefixes even for 0x0fXX opcodes we can remove
the OPC_D16 bit.
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Disjoint instruction types don't need to be a bit field, so
introduce an enumeration (3 bits). Also the 0x0f prefix can
be expressed by a bit, doesn't need a byte in the opcode field.
That enables to encode further prefixes still in 16 bit.
To not have to touch all insns do some macro fiddling filtering
out a 0x0f byte in the second position.
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In particular those that are extensions of existing mmx (or sse1)
instructions by a simple 0x66 prefix. There's one caveat for
x86-64: as we don't yet correctly handle the 0xf3 prefix
the movq mem64->xmm is wrong (tested in asmtest.S). Needs
some refactoring of the instr_type member.
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There were two errors in the arithmetic imm8 instruction. They accept
only REGW, and in case the user write a xxxb opcode that variant
needs to be rejected as well (it's not automatically rejected by REGW
in case the destination is memory).
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Two things: negative constants were rejected (e.g. "add $-15,%eax").
Second the insn order was such that the arithmetic IM8S forms
weren't used (always the IM32 ones). Switching them prefers those
but requires a fix for size calculation in case the opcodes were
OPC_ARITH and OPC_WLX (whose size starts with 1, not zero).
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Use OPC_BWLX and OPC_WLX in i386-asm.h and x86_64-asm.h to
reduce number of differences between both.
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This code was inactive since a long time (and was deactivated because
it was wrong to start with) and just clutters the sources. Remove
it.
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cmov can accept multi sizes, but is also a OPC_TEST opcode,
deal with this.
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A bag of assembler fixes, to be either compatible with GAS
(e.g. order of 'test' operands), accept more instructions,
count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes
on x86_64 to not use %rip relative addressing mode, to not use
invalid insns in tests/asmtest.S for x86_64.
Result is that now output of GAS and of tcc on tests/asmtest.S
is mostly the same.
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Various x86 asm fixes: 64bit lcall/ljmp like 32bit a commit before,
xchgw accepted wrong operands on 32 and 64bit, and 64bit used
0x40/0x48+reg for incw/decw, but those are REX prefixes, not
instructions.
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The 0xff/3 form of lcall needs a mod/rm byte, so reflect this.
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patch from Anaël Seghezzi
a test program:
============================
#include <stdio.h>
struct fl4{ float x, y, z, w; };
void asm_test(void)
{
struct fl4 v1, v2, v3;
v1.x = 0.1;
v1.y = 0.2;
v1.z = 0.4;
v1.w = 0.3;
v2.x = 0.11;
v2.y = 0.0;
v2.z = 0.01;
v2.w = 0.04;
asm volatile (
"movups %0, %%xmm0;"
"movups %1, %%xmm1;"
"addps %%xmm1, %%xmm0;"
"movups %%xmm0, %2"
:: "g" (v1), "g" (v2), "g" (v3) : "memory");
printf("sse fl4 add : %f %f %f %f\n", v3.x, v3.y, v3.z, v3.w);
printf("expected : %f %f %f %f\n", v1.x+v2.x, v1.y+v2.y, v1.z+v2.z, v1.w+v2.w);
}
int main() { asm_test(); }
/*
sse fl4 add : 0.210000 0.200000 0.410000 0.340000
expected : 0.210000 0.200000 0.410000 0.340000
*/
============================
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* Documentation is now in "docs".
* Source code is now in "src".
* Misc. fixes here and there so that everything still works.
I think I got everything in this commit, but I only tested this
on Linux (Make) and Windows (CMake), so I might've messed
something up on other platforms...
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PS: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20101122/112576.html
This is fix PR8686 for llvm: accepting a 'b' suffix at the end
of all the setcc instructions.
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Display a different warning when an instruction is recognized by tcc but
the operands found do not correspond to the constraints of the
instruction.
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Also, disable 16bit support for now as it causes bugs
in 32bit mode. #define I386_ASM_16 if you want it.
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The new 16bit code was causing wrong 0x66 prefixes
in 32bit code.
The fix possibly breaks the feature on 16bit asm.
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