aboutsummaryrefslogtreecommitdiff
path: root/src/arm
diff options
context:
space:
mode:
Diffstat (limited to 'src/arm')
-rw-r--r--src/arm/arm-gen.c2162
-rw-r--r--src/arm/arm64-gen.c1846
2 files changed, 4008 insertions, 0 deletions
diff --git a/src/arm/arm-gen.c b/src/arm/arm-gen.c
new file mode 100644
index 0000000..f31fb88
--- /dev/null
+++ b/src/arm/arm-gen.c
@@ -0,0 +1,2162 @@
+/*
+ * ARMv4 code generator for TCC
+ *
+ * Copyright (c) 2003 Daniel Glöckner
+ * Copyright (c) 2012 Thomas Preud'homme
+ *
+ * Based on i386-gen.c by Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifdef TARGET_DEFS_ONLY
+
+#if defined(TCC_ARM_EABI) && !defined(TCC_ARM_VFP)
+#error "Currently TinyCC only supports float computation with VFP instructions"
+#endif
+
+/* number of available registers */
+#ifdef TCC_ARM_VFP
+#define NB_REGS 13
+#else
+#define NB_REGS 9
+#endif
+
+typedef int RegArgs;
+
+#ifndef TCC_ARM_VERSION
+#define TCC_ARM_VERSION 5
+#endif
+
+/* a register can belong to several classes. The classes must be
+ sorted from more general to more precise (see gv2() code which does
+ assumptions on it). */
+#define RC_INT 0x0001 /* generic integer register */
+#define RC_FLOAT 0x0002 /* generic float register */
+#define RC_R0 0x0004
+#define RC_R1 0x0008
+#define RC_R2 0x0010
+#define RC_R3 0x0020
+#define RC_R12 0x0040
+#define RC_F0 0x0080
+#define RC_F1 0x0100
+#define RC_F2 0x0200
+#define RC_F3 0x0400
+#ifdef TCC_ARM_VFP
+#define RC_F4 0x0800
+#define RC_F5 0x1000
+#define RC_F6 0x2000
+#define RC_F7 0x4000
+#endif
+#define RC_IRET RC_R0 /* function return: integer register */
+#define RC_LRET RC_R1 /* function return: second integer register */
+#define RC_FRET RC_F0 /* function return: float register */
+
+/* pretty names for the registers */
+enum {
+ TREG_R0 = 0,
+ TREG_R1,
+ TREG_R2,
+ TREG_R3,
+ TREG_R12,
+ TREG_F0,
+ TREG_F1,
+ TREG_F2,
+ TREG_F3,
+#ifdef TCC_ARM_VFP
+ TREG_F4,
+ TREG_F5,
+ TREG_F6,
+ TREG_F7,
+#endif
+};
+
+#ifdef TCC_ARM_VFP
+#define T2CPR(t) (((t)&VT_BTYPE) != VT_FLOAT ? 0x100 : 0)
+#endif
+
+/* return registers for function */
+#define REG_IRET TREG_R0 /* single word int return register */
+#define REG_LRET TREG_R1 /* second word return register (for long long) */
+#define REG_FRET TREG_F0 /* float return register */
+
+#ifdef TCC_ARM_EABI
+#define TOK___divdi3 TOK___aeabi_ldivmod
+#define TOK___moddi3 TOK___aeabi_ldivmod
+#define TOK___udivdi3 TOK___aeabi_uldivmod
+#define TOK___umoddi3 TOK___aeabi_uldivmod
+#endif
+
+/* defined if function parameters must be evaluated in reverse order */
+#define INVERT_FUNC_PARAMS
+
+/* defined if structures are passed as pointers. Otherwise structures
+ are directly pushed on stack. */
+/* #define FUNC_STRUCT_PARAM_AS_PTR */
+
+/* pointer size, in bytes */
+#define PTR_SIZE 4
+
+/* long double size and alignment, in bytes */
+#ifdef TCC_ARM_VFP
+#define LDOUBLE_SIZE 8
+#endif
+
+#ifndef LDOUBLE_SIZE
+#define LDOUBLE_SIZE 8
+#endif
+
+#ifdef TCC_ARM_EABI
+#define LDOUBLE_ALIGN 8
+#else
+#define LDOUBLE_ALIGN 4
+#endif
+
+/* maximum alignment (for aligned attribute support) */
+#define MAX_ALIGN 8
+
+#define CHAR_IS_UNSIGNED
+
+/******************************************************/
+/* ELF defines */
+
+#define EM_TCC_TARGET EM_ARM
+
+/* relocation type for 32 bit data relocation */
+#define R_DATA_32 R_ARM_ABS32
+#define R_DATA_PTR R_ARM_ABS32
+#define R_JMP_SLOT R_ARM_JUMP_SLOT
+#define R_COPY R_ARM_COPY
+
+#define ELF_START_ADDR 0x00008000
+#define ELF_PAGE_SIZE 0x1000
+
+enum float_abi {
+ ARM_SOFTFP_FLOAT,
+ ARM_HARD_FLOAT,
+};
+
+/******************************************************/
+#else /* ! TARGET_DEFS_ONLY */
+/******************************************************/
+#include "../tcc.h"
+
+enum float_abi float_abi;
+
+ST_DATA const int reg_classes[NB_REGS] = {
+ /* r0 */ RC_INT | RC_R0,
+ /* r1 */ RC_INT | RC_R1,
+ /* r2 */ RC_INT | RC_R2,
+ /* r3 */ RC_INT | RC_R3,
+ /* r12 */ RC_INT | RC_R12,
+ /* f0 */ RC_FLOAT | RC_F0,
+ /* f1 */ RC_FLOAT | RC_F1,
+ /* f2 */ RC_FLOAT | RC_F2,
+ /* f3 */ RC_FLOAT | RC_F3,
+#ifdef TCC_ARM_VFP
+ /* d4/s8 */ RC_FLOAT | RC_F4,
+ /* d5/s10 */ RC_FLOAT | RC_F5,
+ /* d6/s12 */ RC_FLOAT | RC_F6,
+ /* d7/s14 */ RC_FLOAT | RC_F7,
+#endif
+};
+
+static int func_sub_sp_offset, last_itod_magic;
+static int leaffunc;
+
+#if defined(TCC_ARM_EABI) && defined(TCC_ARM_VFP)
+static CType float_type, double_type, func_float_type, func_double_type;
+ST_FUNC void arm_init(struct TCCState* s)
+{
+ float_type.t = VT_FLOAT;
+ double_type.t = VT_DOUBLE;
+ func_float_type.t = VT_FUNC;
+ func_float_type.ref =
+ sym_push(SYM_FIELD, &float_type, FUNC_CDECL, FUNC_OLD);
+ func_double_type.t = VT_FUNC;
+ func_double_type.ref =
+ sym_push(SYM_FIELD, &double_type, FUNC_CDECL, FUNC_OLD);
+
+ float_abi = s->float_abi;
+#ifndef TCC_ARM_HARDFLOAT
+ tcc_warning("soft float ABI currently not supported: default to softfp");
+#endif
+}
+#else
+#define func_float_type func_old_type
+#define func_double_type func_old_type
+#define func_ldouble_type func_old_type
+ST_FUNC void arm_init(struct TCCState* s)
+{
+#if !defined(TCC_ARM_VFP)
+ tcc_warning("Support for FPA is deprecated and will be removed in next"
+ " release");
+#endif
+#if !defined(TCC_ARM_EABI)
+ tcc_warning("Support for OABI is deprecated and will be removed in next"
+ " release");
+#endif
+}
+#endif
+
+static int two2mask(int a, int b)
+{
+ return (reg_classes[a] | reg_classes[b]) & ~(RC_INT | RC_FLOAT);
+}
+
+static int regmask(int r)
+{
+ return reg_classes[r] & ~(RC_INT | RC_FLOAT);
+}
+
+/******************************************************/
+
+#if defined(TCC_ARM_EABI) && !defined(CONFIG_TCC_ELFINTERP)
+char* default_elfinterp(struct TCCState* s)
+{
+ if (s->float_abi == ARM_HARD_FLOAT)
+ return "/lib/ld-linux-armhf.so.3";
+ else
+ return "/lib/ld-linux.so.3";
+}
+#endif
+
+void o(uint32_t i)
+{
+ /* this is a good place to start adding big-endian support*/
+ int ind1;
+
+ ind1 = ind + 4;
+ if (!cur_text_section)
+ tcc_error("compiler error! This happens f.ex. if the compiler\n"
+ "can't evaluate constant expressions outside of a function.");
+ if (ind1 > cur_text_section->data_allocated)
+ section_realloc(cur_text_section, ind1);
+ cur_text_section->data[ind++] = i & 255;
+ i >>= 8;
+ cur_text_section->data[ind++] = i & 255;
+ i >>= 8;
+ cur_text_section->data[ind++] = i & 255;
+ i >>= 8;
+ cur_text_section->data[ind++] = i;
+}
+
+static uint32_t stuff_const(uint32_t op, uint32_t c)
+{
+ int try_neg = 0;
+ uint32_t nc = 0, negop = 0;
+
+ switch (op & 0x1F00000) {
+ case 0x800000: // add
+ case 0x400000: // sub
+ try_neg = 1;
+ negop = op ^ 0xC00000;
+ nc = -c;
+ break;
+ case 0x1A00000: // mov
+ case 0x1E00000: // mvn
+ try_neg = 1;
+ negop = op ^ 0x400000;
+ nc = ~c;
+ break;
+ case 0x200000: // xor
+ if (c == ~0)
+ return (op & 0xF010F000) | ((op >> 16) & 0xF) | 0x1E00000;
+ break;
+ case 0x0: // and
+ if (c == ~0)
+ return (op & 0xF010F000) | ((op >> 16) & 0xF) | 0x1A00000;
+ case 0x1C00000: // bic
+ try_neg = 1;
+ negop = op ^ 0x1C00000;
+ nc = ~c;
+ break;
+ case 0x1800000: // orr
+ if (c == ~0)
+ return (op & 0xFFF0FFFF) | 0x1E00000;
+ break;
+ }
+ do {
+ uint32_t m;
+ int i;
+ if (c < 256) /* catch undefined <<32 */
+ return op | c;
+ for (i = 2; i < 32; i += 2) {
+ m = (0xff >> i) | (0xff << (32 - i));
+ if (!(c & ~m))
+ return op | (i << 7) | (c << i) | (c >> (32 - i));
+ }
+ op = negop;
+ c = nc;
+ } while (try_neg--);
+ return 0;
+}
+
+// only add,sub
+void stuff_const_harder(uint32_t op, uint32_t v)
+{
+ uint32_t x;
+ x = stuff_const(op, v);
+ if (x)
+ o(x);
+ else {
+ uint32_t a[16], nv, no, o2, n2;
+ int i, j, k;
+ a[0] = 0xff;
+ o2 = (op & 0xfff0ffff) | ((op & 0xf000) << 4);
+ ;
+ for (i = 1; i < 16; i++)
+ a[i] = (a[i - 1] >> 2) | (a[i - 1] << 30);
+ for (i = 0; i < 12; i++)
+ for (j = i < 4 ? i + 12 : 15; j >= i + 4; j--)
+ if ((v & (a[i] | a[j])) == v) {
+ o(stuff_const(op, v & a[i]));
+ o(stuff_const(o2, v & a[j]));
+ return;
+ }
+ no = op ^ 0xC00000;
+ n2 = o2 ^ 0xC00000;
+ nv = -v;
+ for (i = 0; i < 12; i++)
+ for (j = i < 4 ? i + 12 : 15; j >= i + 4; j--)
+ if ((nv & (a[i] | a[j])) == nv) {
+ o(stuff_const(no, nv & a[i]));
+ o(stuff_const(n2, nv & a[j]));
+ return;
+ }
+ for (i = 0; i < 8; i++)
+ for (j = i + 4; j < 12; j++)
+ for (k = i < 4 ? i + 12 : 15; k >= j + 4; k--)
+ if ((v & (a[i] | a[j] | a[k])) == v) {
+ o(stuff_const(op, v & a[i]));
+ o(stuff_const(o2, v & a[j]));
+ o(stuff_const(o2, v & a[k]));
+ return;
+ }
+ no = op ^ 0xC00000;
+ nv = -v;
+ for (i = 0; i < 8; i++)
+ for (j = i + 4; j < 12; j++)
+ for (k = i < 4 ? i + 12 : 15; k >= j + 4; k--)
+ if ((nv & (a[i] | a[j] | a[k])) == nv) {
+ o(stuff_const(no, nv & a[i]));
+ o(stuff_const(n2, nv & a[j]));
+ o(stuff_const(n2, nv & a[k]));
+ return;
+ }
+ o(stuff_const(op, v & a[0]));
+ o(stuff_const(o2, v & a[4]));
+ o(stuff_const(o2, v & a[8]));
+ o(stuff_const(o2, v & a[12]));
+ }
+}
+
+ST_FUNC uint32_t encbranch(int pos, int addr, int fail)
+{
+ addr -= pos + 8;
+ addr /= 4;
+ if (addr >= 0x1000000 || addr < -0x1000000) {
+ if (fail)
+ tcc_error("FIXME: function bigger than 32MB");
+ return 0;
+ }
+ return 0x0A000000 | (addr & 0xffffff);
+}
+
+int decbranch(int pos)
+{
+ int x;
+ x = *(uint32_t*)(cur_text_section->data + pos);
+ x &= 0x00ffffff;
+ if (x & 0x800000)
+ x -= 0x1000000;
+ return x * 4 + pos + 8;
+}
+
+/* output a symbol and patch all calls to it */
+void gsym_addr(int t, int a)
+{
+ uint32_t* x;
+ int lt;
+ while (t) {
+ x = (uint32_t*)(cur_text_section->data + t);
+ t = decbranch(lt = t);
+ if (a == lt + 4)
+ *x = 0xE1A00000; // nop
+ else {
+ *x &= 0xff000000;
+ *x |= encbranch(lt, a, 1);
+ }
+ }
+}
+
+void gsym(int t)
+{
+ gsym_addr(t, ind);
+}
+
+#ifdef TCC_ARM_VFP
+static uint32_t vfpr(int r)
+{
+ if (r < TREG_F0 || r > TREG_F7)
+ tcc_error("compiler error! register %i is no vfp register", r);
+ return r - 5;
+}
+#else
+static uint32_t fpr(int r)
+{
+ if (r < TREG_F0 || r > TREG_F3)
+ tcc_error("compiler error! register %i is no fpa register", r);
+ return r - 5;
+}
+#endif
+
+static uint32_t intr(int r)
+{
+ if (r == 4)
+ return 12;
+ if ((r < 0 || r > 4) && r != 14)
+ tcc_error("compiler error! register %i is no int register", r);
+ return r;
+}
+
+static void calcaddr(uint32_t* base, int* off, int* sgn, int maxoff,
+ unsigned shift)
+{
+ if (*off > maxoff || *off & ((1 << shift) - 1)) {
+ uint32_t x, y;
+ x = 0xE280E000;
+ if (*sgn)
+ x = 0xE240E000;
+ x |= (*base) << 16;
+ *base = 14; // lr
+ y = stuff_const(x, *off & ~maxoff);
+ if (y) {
+ o(y);
+ *off &= maxoff;
+ return;
+ }
+ y = stuff_const(x, (*off + maxoff) & ~maxoff);
+ if (y) {
+ o(y);
+ *sgn = !*sgn;
+ *off = ((*off + maxoff) & ~maxoff) - *off;
+ return;
+ }
+ stuff_const_harder(x, *off & ~maxoff);
+ *off &= maxoff;
+ }
+}
+
+static uint32_t mapcc(int cc)
+{
+ switch (cc) {
+ case TOK_ULT:
+ return 0x30000000; /* CC/LO */
+ case TOK_UGE:
+ return 0x20000000; /* CS/HS */
+ case TOK_EQ:
+ return 0x00000000; /* EQ */
+ case TOK_NE:
+ return 0x10000000; /* NE */
+ case TOK_ULE:
+ return 0x90000000; /* LS */
+ case TOK_UGT:
+ return 0x80000000; /* HI */
+ case TOK_Nset:
+ return 0x40000000; /* MI */
+ case TOK_Nclear:
+ return 0x50000000; /* PL */
+ case TOK_LT:
+ return 0xB0000000; /* LT */
+ case TOK_GE:
+ return 0xA0000000; /* GE */
+ case TOK_LE:
+ return 0xD0000000; /* LE */
+ case TOK_GT:
+ return 0xC0000000; /* GT */
+ }
+ tcc_error("unexpected condition code");
+ return 0xE0000000; /* AL */
+}
+
+static int negcc(int cc)
+{
+ switch (cc) {
+ case TOK_ULT:
+ return TOK_UGE;
+ case TOK_UGE:
+ return TOK_ULT;
+ case TOK_EQ:
+ return TOK_NE;
+ case TOK_NE:
+ return TOK_EQ;
+ case TOK_ULE:
+ return TOK_UGT;
+ case TOK_UGT:
+ return TOK_ULE;
+ case TOK_Nset:
+ return TOK_Nclear;
+ case TOK_Nclear:
+ return TOK_Nset;
+ case TOK_LT:
+ return TOK_GE;
+ case TOK_GE:
+ return TOK_LT;
+ case TOK_LE:
+ return TOK_GT;
+ case TOK_GT:
+ return TOK_LE;
+ }
+ tcc_error("unexpected condition code");
+ return TOK_NE;
+}
+
+/* load 'r' from value 'sv' */
+void load(int r, SValue* sv)
+{
+ int v, ft, fc, fr, sign;
+ uint32_t op;
+ SValue v1;
+
+ fr = sv->r;
+ ft = sv->type.t;
+ fc = sv->c.ul;
+
+ if (fc >= 0)
+ sign = 0;
+ else {
+ sign = 1;
+ fc = -fc;
+ }
+
+ v = fr & VT_VALMASK;
+ if (fr & VT_LVAL) {
+ uint32_t base = 0xB; // fp
+ if (v == VT_LLOCAL) {
+ v1.type.t = VT_PTR;
+ v1.r = VT_LOCAL | VT_LVAL;
+ v1.c.ul = sv->c.ul;
+ load(base = 14 /* lr */, &v1);
+ fc = sign = 0;
+ v = VT_LOCAL;
+ } else if (v == VT_CONST) {
+ v1.type.t = VT_PTR;
+ v1.r = fr & ~VT_LVAL;
+ v1.c.ul = sv->c.ul;
+ v1.sym = sv->sym;
+ load(base = 14, &v1);
+ fc = sign = 0;
+ v = VT_LOCAL;
+ } else if (v < VT_CONST) {
+ base = intr(v);
+ fc = sign = 0;
+ v = VT_LOCAL;
+ }
+ if (v == VT_LOCAL) {
+ if (is_float(ft)) {
+ calcaddr(&base, &fc, &sign, 1020, 2);
+#ifdef TCC_ARM_VFP
+ op = 0xED100A00; /* flds */
+ if (!sign)
+ op |= 0x800000;
+ if ((ft & VT_BTYPE) != VT_FLOAT)
+ op |= 0x100; /* flds -> fldd */
+ o(op | (vfpr(r) << 12) | (fc >> 2) | (base << 16));
+#else
+ op = 0xED100100;
+ if (!sign)
+ op |= 0x800000;
+#if LDOUBLE_SIZE == 8
+ if ((ft & VT_BTYPE) != VT_FLOAT)
+ op |= 0x8000;
+#else
+ if ((ft & VT_BTYPE) == VT_DOUBLE)
+ op |= 0x8000;
+ else if ((ft & VT_BTYPE) == VT_LDOUBLE)
+ op |= 0x400000;
+#endif
+ o(op | (fpr(r) << 12) | (fc >> 2) | (base << 16));
+#endif
+ } else if ((ft & (VT_BTYPE | VT_UNSIGNED)) == VT_BYTE ||
+ (ft & VT_BTYPE) == VT_SHORT) {
+ calcaddr(&base, &fc, &sign, 255, 0);
+ op = 0xE1500090;
+ if ((ft & VT_BTYPE) == VT_SHORT)
+ op |= 0x20;
+ if ((ft & VT_UNSIGNED) == 0)
+ op |= 0x40;
+ if (!sign)
+ op |= 0x800000;
+ o(op | (intr(r) << 12) | (base << 16) | ((fc & 0xf0) << 4) |
+ (fc & 0xf));
+ } else {
+ calcaddr(&base, &fc, &sign, 4095, 0);
+ op = 0xE5100000;
+ if (!sign)
+ op |= 0x800000;
+ if ((ft & VT_BTYPE) == VT_BYTE || (ft & VT_BTYPE) == VT_BOOL)
+ op |= 0x400000;
+ o(op | (intr(r) << 12) | fc | (base << 16));
+ }
+ return;
+ }
+ } else {
+ if (v == VT_CONST) {
+ op = stuff_const(0xE3A00000 | (intr(r) << 12), sv->c.ul);
+ if (fr & VT_SYM || !op) {
+ o(0xE59F0000 | (intr(r) << 12));
+ o(0xEA000000);
+ if (fr & VT_SYM)
+ greloc(cur_text_section, sv->sym, ind, R_ARM_ABS32);
+ o(sv->c.ul);
+ } else
+ o(op);
+ return;
+ } else if (v == VT_LOCAL) {
+ op = stuff_const(0xE28B0000 | (intr(r) << 12), sv->c.ul);
+ if (fr & VT_SYM || !op) {
+ o(0xE59F0000 | (intr(r) << 12));
+ o(0xEA000000);
+ if (fr & VT_SYM) // needed ?
+ greloc(cur_text_section, sv->sym, ind, R_ARM_ABS32);
+ o(sv->c.ul);
+ o(0xE08B0000 | (intr(r) << 12) | intr(r));
+ } else
+ o(op);
+ return;
+ } else if (v == VT_CMP) {
+ o(mapcc(sv->c.ul) | 0x3A00001 | (intr(r) << 12));
+ o(mapcc(negcc(sv->c.ul)) | 0x3A00000 | (intr(r) << 12));
+ return;
+ } else if (v == VT_JMP || v == VT_JMPI) {
+ int t;
+ t = v & 1;
+ o(0xE3A00000 | (intr(r) << 12) | t);
+ o(0xEA000000);
+ gsym(sv->c.ul);
+ o(0xE3A00000 | (intr(r) << 12) | (t ^ 1));
+ return;
+ } else if (v < VT_CONST) {
+ if (is_float(ft))
+#ifdef TCC_ARM_VFP
+ o(0xEEB00A40 | (vfpr(r) << 12) | vfpr(v) |
+ T2CPR(ft)); /* fcpyX */
+#else
+ o(0xEE008180 | (fpr(r) << 12) | fpr(v));
+#endif
+ else
+ o(0xE1A00000 | (intr(r) << 12) | intr(v));
+ return;
+ }
+ }
+ tcc_error("load unimplemented!");
+}
+
+/* store register 'r' in lvalue 'v' */
+void store(int r, SValue* sv)
+{
+ SValue v1;
+ int v, ft, fc, fr, sign;
+ uint32_t op;
+
+ fr = sv->r;
+ ft = sv->type.t;
+ fc = sv->c.ul;
+
+ if (fc >= 0)
+ sign = 0;
+ else {
+ sign = 1;
+ fc = -fc;
+ }
+
+ v = fr & VT_VALMASK;
+ if (fr & VT_LVAL || fr == VT_LOCAL) {
+ uint32_t base = 0xb;
+ if (v < VT_CONST) {
+ base = intr(v);
+ v = VT_LOCAL;
+ fc = sign = 0;
+ } else if (v == VT_CONST) {
+ v1.type.t = ft;
+ v1.r = fr & ~VT_LVAL;
+ v1.c.ul = sv->c.ul;
+ v1.sym = sv->sym;
+ load(base = 14, &v1);
+ fc = sign = 0;
+ v = VT_LOCAL;
+ }
+ if (v == VT_LOCAL) {
+ if (is_float(ft)) {
+ calcaddr(&base, &fc, &sign, 1020, 2);
+#ifdef TCC_ARM_VFP
+ op = 0xED000A00; /* fsts */
+ if (!sign)
+ op |= 0x800000;
+ if ((ft & VT_BTYPE) != VT_FLOAT)
+ op |= 0x100; /* fsts -> fstd */
+ o(op | (vfpr(r) << 12) | (fc >> 2) | (base << 16));
+#else
+ op = 0xED000100;
+ if (!sign)
+ op |= 0x800000;
+#if LDOUBLE_SIZE == 8
+ if ((ft & VT_BTYPE) != VT_FLOAT)
+ op |= 0x8000;
+#else
+ if ((ft & VT_BTYPE) == VT_DOUBLE)
+ op |= 0x8000;
+ if ((ft & VT_BTYPE) == VT_LDOUBLE)
+ op |= 0x400000;
+#endif
+ o(op | (fpr(r) << 12) | (fc >> 2) | (base << 16));
+#endif
+ return;
+ } else if ((ft & VT_BTYPE) == VT_SHORT) {
+ calcaddr(&base, &fc, &sign, 255, 0);
+ op = 0xE14000B0;
+ if (!sign)
+ op |= 0x800000;
+ o(op | (intr(r) << 12) | (base << 16) | ((fc & 0xf0) << 4) |
+ (fc & 0xf));
+ } else {
+ calcaddr(&base, &fc, &sign, 4095, 0);
+ op = 0xE5000000;
+ if (!sign)
+ op |= 0x800000;
+ if ((ft & VT_BTYPE) == VT_BYTE || (ft & VT_BTYPE) == VT_BOOL)
+ op |= 0x400000;
+ o(op | (intr(r) << 12) | fc | (base << 16));
+ }
+ return;
+ }
+ }
+ tcc_error("store unimplemented");
+}
+
+static void gadd_sp(int val)
+{
+ stuff_const_harder(0xE28DD000, val);
+}
+
+/* 'is_jmp' is '1' if it is a jump */
+static void gcall_or_jmp(int is_jmp)
+{
+ int r;
+ if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
+ uint32_t x;
+ /* constant case */
+ x = encbranch(ind, ind + vtop->c.ul, 0);
+ if (x) {
+ if (vtop->r & VT_SYM) {
+ /* relocation case */
+ greloc(cur_text_section, vtop->sym, ind, R_ARM_PC24);
+ } else
+ put_elf_reloc(symtab_section, cur_text_section, ind, R_ARM_PC24,
+ 0);
+ o(x | (is_jmp ? 0xE0000000 : 0xE1000000));
+ } else {
+ if (!is_jmp)
+ o(0xE28FE004); // add lr,pc,#4
+ o(0xE51FF004); // ldr pc,[pc,#-4]
+ if (vtop->r & VT_SYM)
+ greloc(cur_text_section, vtop->sym, ind, R_ARM_ABS32);
+ o(vtop->c.ul);
+ }
+ } else {
+ /* otherwise, indirect call */
+ r = gv(RC_INT);
+ if (!is_jmp)
+ o(0xE1A0E00F); // mov lr,pc
+ o(0xE1A0F000 | intr(r)); // mov pc,r
+ }
+}
+
+/* Return whether a structure is an homogeneous float aggregate or not.
+ The answer is true if all the elements of the structure are of the same
+ primitive float type and there is less than 4 elements.
+
+ type: the type corresponding to the structure to be tested */
+static int is_hgen_float_aggr(CType* type)
+{
+ if ((type->t & VT_BTYPE) == VT_STRUCT) {
+ struct Sym* ref;
+ int btype, nb_fields = 0;
+
+ ref = type->ref->next;
+ btype = ref->type.t & VT_BTYPE;
+ if (btype == VT_FLOAT || btype == VT_DOUBLE) {
+ for (; ref && btype == (ref->type.t & VT_BTYPE);
+ ref = ref->next, nb_fields++)
+ ;
+ return !ref && nb_fields <= 4;
+ }
+ }
+ return 0;
+}
+
+struct avail_regs {
+ signed char
+ avail[3]; /* 3 holes max with only float and double alignments */
+ int first_hole; /* first available hole */
+ int last_hole; /* last available hole (none if equal to first_hole) */
+ int first_free_reg; /* next free register in the sequence, hole excluded */
+};
+
+#define AVAIL_REGS_INITIALIZER (struct avail_regs) { { 0, 0, 0}, 0, 0, 0 }
+
+/* Find suitable registers for a VFP Co-Processor Register Candidate (VFP CPRC
+ param) according to the rules described in the procedure call standard for
+ the ARM architecture (AAPCS). If found, the registers are assigned to this
+ VFP CPRC parameter. Registers are allocated in sequence unless a hole exists
+ and the parameter is a single float.
+
+ avregs: opaque structure to keep track of available VFP co-processor regs
+ align: alignment contraints for the param, as returned by type_size()
+ size: size of the parameter, as returned by type_size() */
+int assign_vfpreg(struct avail_regs* avregs, int align, int size)
+{
+ int first_reg = 0;
+
+ if (avregs->first_free_reg == -1)
+ return -1;
+ if (align >> 3) { /* double alignment */
+ first_reg = avregs->first_free_reg;
+ /* alignment contraint not respected so use next reg and record hole */
+ if (first_reg & 1)
+ avregs->avail[avregs->last_hole++] = first_reg++;
+ } else { /* no special alignment (float or array of float) */
+ /* if single float and a hole is available, assign the param to it */
+ if (size == 4 && avregs->first_hole != avregs->last_hole)
+ return avregs->avail[avregs->first_hole++];
+ else
+ first_reg = avregs->first_free_reg;
+ }
+ if (first_reg + size / 4 <= 16) {
+ avregs->first_free_reg = first_reg + size / 4;
+ return first_reg;
+ }
+ avregs->first_free_reg = -1;
+ return -1;
+}
+
+/* Returns whether all params need to be passed in core registers or not.
+ This is the case for function part of the runtime ABI. */
+int floats_in_core_regs(SValue* sval)
+{
+ if (!sval->sym)
+ return 0;
+
+ switch (sval->sym->v) {
+ case TOK___floatundisf:
+ case TOK___floatundidf:
+ case TOK___fixunssfdi:
+ case TOK___fixunsdfdi:
+#ifndef TCC_ARM_VFP
+ case TOK___fixunsxfdi:
+#endif
+ case TOK___floatdisf:
+ case TOK___floatdidf:
+ case TOK___fixsfdi:
+ case TOK___fixdfdi:
+ return 1;
+
+ default:
+ return 0;
+ }
+}
+
+ST_FUNC int regargs_nregs(RegArgs* args)
+{
+ return *args;
+}
+
+/* Return the number of registers needed to return the struct, or 0 if
+ returning via struct pointer. */
+ST_FUNC int gfunc_sret(CType* vt, int variadic, CType* ret, int* ret_align,
+ int* regsize, RegArgs* args)
+{
+#ifdef TCC_ARM_EABI
+ int size, align;
+ size = type_size(vt, &align);
+ if (float_abi == ARM_HARD_FLOAT && !variadic &&
+ (is_float(vt->t) || is_hgen_float_aggr(vt))) {
+ *ret_align = 8;
+ *regsize = 8;
+ ret->ref = NULL;
+ ret->t = VT_DOUBLE;
+ *args = (size + 7) >> 3;
+ } else if (size <= 4) {
+ *ret_align = 4;
+ *regsize = 4;
+ ret->ref = NULL;
+ ret->t = VT_INT;
+ *args = 1;
+ } else
+ *args = 0;
+#else
+ *args = 0;
+#endif
+
+ return *args != 0;
+}
+
+/* Parameters are classified according to how they are copied to their final
+ destination for the function call. Because the copying is performed class
+ after class according to the order in the union below, it is important that
+ some constraints about the order of the members of this union are respected:
+ - CORE_STRUCT_CLASS must come after STACK_CLASS;
+ - CORE_CLASS must come after STACK_CLASS, CORE_STRUCT_CLASS and
+ VFP_STRUCT_CLASS;
+ - VFP_STRUCT_CLASS must come after VFP_CLASS.
+ See the comment for the main loop in copy_params() for the reason. */
+enum reg_class {
+ STACK_CLASS = 0,
+ CORE_STRUCT_CLASS,
+ VFP_CLASS,
+ VFP_STRUCT_CLASS,
+ CORE_CLASS,
+ NB_CLASSES
+};
+
+struct param_plan {
+ int start; /* first reg or addr used depending on the class */
+ int end; /* last reg used or next free addr depending on the class */
+ SValue* sval; /* pointer to SValue on the value stack */
+ struct param_plan* prev; /* previous element in this class */
+};
+
+struct plan {
+ struct param_plan* pplans; /* array of all the param plans */
+ struct param_plan*
+ clsplans[NB_CLASSES]; /* per class lists of param plans */
+};
+
+#define add_param_plan(plan, pplan, class) \
+ do { \
+ pplan.prev = plan->clsplans[class]; \
+ plan->pplans[plan##_nb] = pplan; \
+ plan->clsplans[class] = &plan->pplans[plan##_nb++]; \
+ } while (0)
+
+/* Assign parameters to registers and stack with alignment according to the
+ rules in the procedure call standard for the ARM architecture (AAPCS).
+ The overall assignment is recorded in an array of per parameter structures
+ called parameter plans. The parameter plans are also further organized in a
+ number of linked lists, one per class of parameter (see the comment for the
+ definition of union reg_class).
+
+ nb_args: number of parameters of the function for which a call is generated
+ float_abi: float ABI in use for this function call
+ plan: the structure where the overall assignment is recorded
+ todo: a bitmap that record which core registers hold a parameter
+
+ Returns the amount of stack space needed for parameter passing
+
+ Note: this function allocated an array in plan->pplans with tcc_malloc. It
+ is the responsibility of the caller to free this array once used (ie not
+ before copy_params). */
+static int assign_regs(int nb_args, int float_abi, struct plan* plan, int* todo)
+{
+ int i, size, align;
+ int ncrn /* next core register number */,
+ nsaa /* next stacked argument address*/;
+ int plan_nb = 0;
+ struct param_plan pplan;
+ struct avail_regs avregs = AVAIL_REGS_INITIALIZER;
+
+ ncrn = nsaa = 0;
+ *todo = 0;
+ plan->pplans = tcc_malloc(nb_args * sizeof(*plan->pplans));
+ memset(plan->clsplans, 0, sizeof(plan->clsplans));
+ for (i = nb_args; i--;) {
+ int j, start_vfpreg = 0;
+ CType type = vtop[-i].type;
+ type.t &= ~VT_ARRAY;
+ size = type_size(&type, &align);
+ size = (size + 3) & ~3;
+ align = (align + 3) & ~3;
+ switch (vtop[-i].type.t & VT_BTYPE) {
+ case VT_STRUCT:
+ case VT_FLOAT:
+ case VT_DOUBLE:
+ case VT_LDOUBLE:
+ if (float_abi == ARM_HARD_FLOAT) {
+ int is_hfa = 0; /* Homogeneous float aggregate */
+
+ if (is_float(vtop[-i].type.t) ||
+ (is_hfa = is_hgen_float_aggr(&vtop[-i].type))) {
+ int end_vfpreg;
+
+ start_vfpreg = assign_vfpreg(&avregs, align, size);
+ end_vfpreg = start_vfpreg + ((size - 1) >> 2);
+ if (start_vfpreg >= 0) {
+ pplan = (struct param_plan){start_vfpreg, end_vfpreg,
+ &vtop[-i]};
+ if (is_hfa)
+ add_param_plan(plan, pplan, VFP_STRUCT_CLASS);
+ else
+ add_param_plan(plan, pplan, VFP_CLASS);
+ continue;
+ } else
+ break;
+ }
+ }
+ ncrn = (ncrn + (align - 1) / 4) & ~((align / 4) - 1);
+ if (ncrn + size / 4 <= 4 || (ncrn < 4 && start_vfpreg != -1)) {
+ /* The parameter is allocated both in core register and on
+ * stack. As
+ * such, it can be of either class: it would either be the last of
+ * CORE_STRUCT_CLASS or the first of STACK_CLASS. */
+ for (j = ncrn; j < 4 && j < ncrn + size / 4; j++)
+ *todo |= (1 << j);
+ pplan = (struct param_plan){ncrn, j, &vtop[-i]};
+ add_param_plan(plan, pplan, CORE_STRUCT_CLASS);
+ ncrn += size / 4;
+ if (ncrn > 4)
+ nsaa = (ncrn - 4) * 4;
+ } else {
+ ncrn = 4;
+ break;
+ }
+ continue;
+ default:
+ if (ncrn < 4) {
+ int is_long = (vtop[-i].type.t & VT_BTYPE) == VT_LLONG;
+
+ if (is_long) {
+ ncrn = (ncrn + 1) & -2;
+ if (ncrn == 4)
+ break;
+ }
+ pplan = (struct param_plan){ncrn, ncrn, &vtop[-i]};
+ ncrn++;
+ if (is_long)
+ pplan.end = ncrn++;
+ add_param_plan(plan, pplan, CORE_CLASS);
+ continue;
+ }
+ }
+ nsaa = (nsaa + (align - 1)) & ~(align - 1);
+ pplan = (struct param_plan){nsaa, nsaa + size, &vtop[-i]};
+ add_param_plan(plan, pplan, STACK_CLASS);
+ nsaa += size; /* size already rounded up before */
+ }
+ return nsaa;
+}
+
+#undef add_param_plan
+
+/* Copy parameters to their final destination (core reg, VFP reg or stack) for
+ function call.
+
+ nb_args: number of parameters the function take
+ plan: the overall assignment plan for parameters
+ todo: a bitmap indicating what core reg will hold a parameter
+
+ Returns the number of SValue added by this function on the value stack */
+static int copy_params(int nb_args, struct plan* plan, int todo)
+{
+ int size, align, r, i, nb_extra_sval = 0;
+ struct param_plan* pplan;
+
+ /* Several constraints require parameters to be copied in a specific order:
+ - structures are copied to the stack before being loaded in a reg;
+ - floats loaded to an odd numbered VFP reg are first copied to the
+ preceding even numbered VFP reg and then moved to the next VFP reg.
+
+ It is thus important that:
+ - structures assigned to core regs must be copied after parameters
+ assigned to the stack but before structures assigned to VFP regs
+ because a structure can lie partly in core registers and partly on
+ the stack;
+ - parameters assigned to the stack and all structures be copied before
+ parameters assigned to a core reg since copying a parameter to the
+ stack require using a core reg;
+ - parameters assigned to VFP regs be copied before structures assigned to
+ VFP regs as the copy might use an even numbered VFP reg that already
+ holds part of a structure. */
+ for (i = 0; i < NB_CLASSES; i++) {
+ for (pplan = plan->clsplans[i]; pplan; pplan = pplan->prev) {
+ vpushv(pplan->sval);
+ pplan->sval->r = pplan->sval->r2 = VT_CONST; /* disable entry */
+ switch (i) {
+ case STACK_CLASS:
+ case CORE_STRUCT_CLASS:
+ case VFP_STRUCT_CLASS:
+ if ((pplan->sval->type.t & VT_BTYPE) == VT_STRUCT) {
+ int padding = 0;
+ size = type_size(&pplan->sval->type, &align);
+ /* align to stack align size */
+ size = (size + 3) & ~3;
+ if (i == STACK_CLASS && pplan->prev)
+ padding = pplan->start - pplan->prev->end;
+ size += padding; /* Add padding if any */
+ /* allocate the necessary size on stack */
+ gadd_sp(-size);
+ /* generate structure store */
+ r = get_reg(RC_INT);
+ o(0xE28D0000 | (intr(r) << 12) |
+ padding); /* add r, sp, padding */
+ vset(&vtop->type, r | VT_LVAL, 0);
+ vswap();
+ vstore(); /* memcpy to current sp + potential padding */
+
+ /* Homogeneous float aggregate are loaded to VFP registers
+ immediately since there is no way of loading data in
+ multiple non consecutive VFP registers as what is done
+ for other structures (see the use of todo). */
+ if (i == VFP_STRUCT_CLASS) {
+ int first = pplan->start, nb = pplan->end - first + 1;
+ /* vpop.32 {pplan->start, ..., pplan->end} */
+ o(0xECBD0A00 | (first & 1) << 22 | (first >> 1) << 12 |
+ nb);
+ /* No need to write the register used to a SValue since
+ VFP regs cannot be used for gcall_or_jmp */
+ }
+ } else {
+ if (is_float(pplan->sval->type.t)) {
+#ifdef TCC_ARM_VFP
+ r = vfpr(gv(RC_FLOAT)) << 12;
+ if ((pplan->sval->type.t & VT_BTYPE) == VT_FLOAT)
+ size = 4;
+ else {
+ size = 8;
+ r |= 0x101; /* vpush.32 -> vpush.64 */
+ }
+ o(0xED2D0A01 + r); /* vpush */
+#else
+ r = fpr(gv(RC_FLOAT)) << 12;
+ if ((pplan->sval->type.t & VT_BTYPE) == VT_FLOAT)
+ size = 4;
+ else if ((pplan->sval->type.t & VT_BTYPE) == VT_DOUBLE)
+ size = 8;
+ else
+ size = LDOUBLE_SIZE;
+
+ if (size == 12)
+ r |= 0x400000;
+ else if (size == 8)
+ r |= 0x8000;
+
+ o(0xED2D0100 | r | (size >> 2)); /* some kind of vpush for FPA */
+#endif
+ } else {
+ /* simple type (currently always same size) */
+ /* XXX: implicit cast ? */
+ size = 4;
+ if ((pplan->sval->type.t & VT_BTYPE) == VT_LLONG) {
+ lexpand_nr();
+ size = 8;
+ r = gv(RC_INT);
+ o(0xE52D0004 | (intr(r) << 12)); /* push r */
+ vtop--;
+ }
+ r = gv(RC_INT);
+ o(0xE52D0004 | (intr(r) << 12)); /* push r */
+ }
+ if (i == STACK_CLASS && pplan->prev)
+ gadd_sp(pplan->prev->end -
+ pplan->start); /* Add padding if any */
+ }
+ break;
+
+ case VFP_CLASS:
+ gv(regmask(TREG_F0 + (pplan->start >> 1)));
+ if (pplan->start &
+ 1) { /* Must be in upper part of double register */
+ o(0xEEF00A40 | ((pplan->start >> 1) << 12) |
+ (pplan->start >> 1)); /* vmov.f32 s(n+1), sn */
+ vtop->r =
+ VT_CONST; /* avoid being saved on stack by gv for next
+ float */
+ }
+ break;
+
+ case CORE_CLASS:
+ if ((pplan->sval->type.t & VT_BTYPE) == VT_LLONG) {
+ lexpand_nr();
+ gv(regmask(pplan->end));
+ pplan->sval->r2 = vtop->r;
+ vtop--;
+ }
+ gv(regmask(pplan->start));
+ /* Mark register as used so that gcall_or_jmp use another one
+ (regs >=4 are free as never used to pass parameters) */
+ pplan->sval->r = vtop->r;
+ break;
+ }
+ vtop--;
+ }
+ }
+
+ /* Manually free remaining registers since next parameters are loaded
+ * manually, without the help of gv(int). */
+ save_regs(nb_args);
+
+ if (todo) {
+ o(0xE8BD0000 | todo); /* pop {todo} */
+ for (pplan = plan->clsplans[CORE_STRUCT_CLASS]; pplan;
+ pplan = pplan->prev) {
+ int r;
+ pplan->sval->r = pplan->start;
+ /* An SValue can only pin 2 registers at best (r and r2) but a
+ structure can occupy more than 2 registers. Thus, we need to
+ push on the value stack some fake parameter to have on SValue
+ for each registers used by a structure (r2 is not used). */
+ for (r = pplan->start + 1; r <= pplan->end; r++) {
+ if (todo & (1 << r)) {
+ nb_extra_sval++;
+ vpushi(0);
+ vtop->r = r;
+ }
+ }
+ }
+ }
+ return nb_extra_sval;
+}
+
+/* Generate function call. The function address is pushed first, then
+ all the parameters in call order. This functions pops all the
+ parameters and the function address. */
+void gfunc_call(int nb_args)
+{
+ int r, args_size;
+ int def_float_abi = float_abi;
+ int todo;
+ struct plan plan;
+
+#ifdef TCC_ARM_EABI
+ int variadic;
+
+ if (float_abi == ARM_HARD_FLOAT) {
+ variadic = (vtop[-nb_args].type.ref->c == FUNC_ELLIPSIS);
+ if (variadic || floats_in_core_regs(&vtop[-nb_args]))
+ float_abi = ARM_SOFTFP_FLOAT;
+ }
+#endif
+ /* cannot let cpu flags if other instruction are generated. Also avoid
+ leaving VT_JMP anywhere except on the top of the stack because it
+ would complicate the code generator. */
+ r = vtop->r & VT_VALMASK;
+ if (r == VT_CMP || (r & ~1) == VT_JMP)
+ gv(RC_INT);
+
+ args_size = assign_regs(nb_args, float_abi, &plan, &todo);
+
+#ifdef TCC_ARM_EABI
+ if (args_size & 7) { /* Stack must be 8 byte aligned at fct call for EABI */
+ args_size = (args_size + 7) & ~7;
+ o(0xE24DD004); /* sub sp, sp, #4 */
+ }
+#endif
+
+ nb_args += copy_params(nb_args, &plan, todo);
+ tcc_free(plan.pplans);
+
+ /* Move fct SValue on top as required by gcall_or_jmp */
+ vrotb(nb_args + 1);
+ gcall_or_jmp(0);
+ if (args_size)
+ gadd_sp(args_size); /* pop all parameters passed on the stack */
+#if defined(TCC_ARM_EABI) && defined(TCC_ARM_VFP)
+ if (float_abi == ARM_SOFTFP_FLOAT && is_float(vtop->type.ref->type.t)) {
+ if ((vtop->type.ref->type.t & VT_BTYPE) == VT_FLOAT) {
+ o(0xEE000A10); /*vmov s0, r0 */
+ } else {
+ o(0xEE000B10); /* vmov.32 d0[0], r0 */
+ o(0xEE201B10); /* vmov.32 d0[1], r1 */
+ }
+ }
+#endif
+ vtop -= nb_args + 1; /* Pop all params and fct address from value stack */
+ leaffunc =
+ 0; /* we are calling a function, so we aren't in a leaf function */
+ float_abi = def_float_abi;
+}
+
+/* generate function prolog of type 't' */
+void gfunc_prolog(CType* func_type)
+{
+ Sym* sym, *sym2;
+ int n, nf, size, align, rs, struct_ret = 0;
+ int addr, pn, sn; /* pn=core, sn=stack */
+ CType ret_type;
+ RegArgs dummy;
+
+#ifdef TCC_ARM_EABI
+ struct avail_regs avregs = AVAIL_REGS_INITIALIZER;
+#endif
+
+ sym = func_type->ref;
+ func_vt = sym->type;
+ func_var = (func_type->ref->c == FUNC_ELLIPSIS);
+
+ n = nf = 0;
+ if ((func_vt.t & VT_BTYPE) == VT_STRUCT &&
+ !gfunc_sret(&func_vt, func_var, &ret_type, &align, &rs, &dummy)) {
+ n++;
+ struct_ret = 1;
+ func_vc = 12; /* Offset from fp of the place to store the result */
+ }
+ for (sym2 = sym->next; sym2 && (n < 4 || nf < 16); sym2 = sym2->next) {
+ size = type_size(&sym2->type, &align);
+#ifdef TCC_ARM_EABI
+ if (float_abi == ARM_HARD_FLOAT && !func_var &&
+ (is_float(sym2->type.t) || is_hgen_float_aggr(&sym2->type))) {
+ int tmpnf = assign_vfpreg(&avregs, align, size);
+ tmpnf += (size + 3) / 4;
+ nf = (tmpnf > nf) ? tmpnf : nf;
+ } else
+#endif
+ if (n < 4)
+ n += (size + 3) / 4;
+ }
+ o(0xE1A0C00D); /* mov ip,sp */
+ if (func_var)
+ n = 4;
+ if (n) {
+ if (n > 4)
+ n = 4;
+#ifdef TCC_ARM_EABI
+ n = (n + 1) & -2;
+#endif
+ o(0xE92D0000 | ((1 << n) - 1)); /* save r0-r4 on stack if needed */
+ }
+ if (nf) {
+ if (nf > 16)
+ nf = 16;
+ nf = (nf + 1) & -2; /* nf => HARDFLOAT => EABI */
+ o(0xED2D0A00 | nf); /* save s0-s15 on stack if needed */
+ }
+ o(0xE92D5800); /* save fp, ip, lr */
+ o(0xE1A0B00D); /* mov fp, sp */
+ func_sub_sp_offset = ind;
+ o(0xE1A00000); /* nop, leave space for stack adjustment in epilog */
+
+#ifdef TCC_ARM_EABI
+ if (float_abi == ARM_HARD_FLOAT) {
+ func_vc += nf * 4;
+ avregs = AVAIL_REGS_INITIALIZER;
+ }
+#endif
+ pn = struct_ret, sn = 0;
+ while ((sym = sym->next)) {
+ CType* type;
+ type = &sym->type;
+ size = type_size(type, &align);
+ size = (size + 3) >> 2;
+ align = (align + 3) & ~3;
+#ifdef TCC_ARM_EABI
+ if (float_abi == ARM_HARD_FLOAT && !func_var &&
+ (is_float(sym->type.t) || is_hgen_float_aggr(&sym->type))) {
+ int fpn = assign_vfpreg(&avregs, align, size << 2);
+ if (fpn >= 0)
+ addr = fpn * 4;
+ else
+ goto from_stack;
+ } else
+#endif
+ if (pn < 4) {
+#ifdef TCC_ARM_EABI
+ pn = (pn + (align - 1) / 4) & -(align / 4);
+#endif
+ addr = (nf + pn) * 4;
+ pn += size;
+ if (!sn && pn > 4)
+ sn = (pn - 4);
+ } else {
+#ifdef TCC_ARM_EABI
+ from_stack:
+ sn = (sn + (align - 1) / 4) & -(align / 4);
+#endif
+ addr = (n + nf + sn) * 4;
+ sn += size;
+ }
+ sym_push(sym->v & ~SYM_FIELD, type, VT_LOCAL | lvalue_type(type->t),
+ addr + 12);
+ }
+ last_itod_magic = 0;
+ leaffunc = 1;
+ loc = 0;
+}
+
+/* generate function epilog */
+void gfunc_epilog(void)
+{
+ uint32_t x;
+ int diff;
+/* Copy float return value to core register if base standard is used and
+ float computation is made with VFP */
+#if defined(TCC_ARM_EABI) && defined(TCC_ARM_VFP)
+ if ((float_abi == ARM_SOFTFP_FLOAT || func_var) && is_float(func_vt.t)) {
+ if ((func_vt.t & VT_BTYPE) == VT_FLOAT)
+ o(0xEE100A10); /* fmrs r0, s0 */
+ else {
+ o(0xEE100B10); /* fmrdl r0, d0 */
+ o(0xEE301B10); /* fmrdh r1, d0 */
+ }
+ }
+#endif
+ o(0xE89BA800); /* restore fp, sp, pc */
+ diff = (-loc + 3) & -4;
+#ifdef TCC_ARM_EABI
+ if (!leaffunc)
+ diff = ((diff + 11) & -8) - 4;
+#endif
+ if (diff > 0) {
+ x = stuff_const(0xE24BD000, diff); /* sub sp,fp,# */
+ if (x)
+ *(uint32_t*)(cur_text_section->data + func_sub_sp_offset) = x;
+ else {
+ int addr;
+ addr = ind;
+ o(0xE59FC004); /* ldr ip,[pc+4] */
+ o(0xE04BD00C); /* sub sp,fp,ip */
+ o(0xE1A0F00E); /* mov pc,lr */
+ o(diff);
+ *(uint32_t*)(cur_text_section->data + func_sub_sp_offset) =
+ 0xE1000000 | encbranch(func_sub_sp_offset, addr, 1);
+ }
+ }
+}
+
+/* generate a jump to a label */
+int gjmp(int t)
+{
+ int r;
+ r = ind;
+ o(0xE0000000 | encbranch(r, t, 1));
+ return r;
+}
+
+/* generate a jump to a fixed address */
+void gjmp_addr(int a)
+{
+ gjmp(a);
+}
+
+/* generate a test. set 'inv' to invert test. Stack entry is popped */
+int gtst(int inv, int t)
+{
+ int v, r;
+ uint32_t op;
+ v = vtop->r & VT_VALMASK;
+ r = ind;
+ if (v == VT_CMP) {
+ op = mapcc(inv ? negcc(vtop->c.i) : vtop->c.i);
+ op |= encbranch(r, t, 1);
+ o(op);
+ t = r;
+ } else if (v == VT_JMP || v == VT_JMPI) {
+ if ((v & 1) == inv) {
+ if (!vtop->c.i)
+ vtop->c.i = t;
+ else {
+ uint32_t* x;
+ int p, lp;
+ if (t) {
+ p = vtop->c.i;
+ do {
+ p = decbranch(lp = p);
+ } while (p);
+ x = (uint32_t*)(cur_text_section->data + lp);
+ *x &= 0xff000000;
+ *x |= encbranch(lp, t, 1);
+ }
+ t = vtop->c.i;
+ }
+ } else {
+ t = gjmp(t);
+ gsym(vtop->c.i);
+ }
+ }
+ vtop--;
+ return t;
+}
+
+/* generate an integer binary operation */
+void gen_opi(int op)
+{
+ int c, func = 0;
+ uint32_t opc = 0, r, fr;
+ unsigned short retreg = REG_IRET;
+
+ c = 0;
+ switch (op) {
+ case '+':
+ opc = 0x8;
+ c = 1;
+ break;
+ case TOK_ADDC1: /* add with carry generation */
+ opc = 0x9;
+ c = 1;
+ break;
+ case '-':
+ opc = 0x4;
+ c = 1;
+ break;
+ case TOK_SUBC1: /* sub with carry generation */
+ opc = 0x5;
+ c = 1;
+ break;
+ case TOK_ADDC2: /* add with carry use */
+ opc = 0xA;
+ c = 1;
+ break;
+ case TOK_SUBC2: /* sub with carry use */
+ opc = 0xC;
+ c = 1;
+ break;
+ case '&':
+ opc = 0x0;
+ c = 1;
+ break;
+ case '^':
+ opc = 0x2;
+ c = 1;
+ break;
+ case '|':
+ opc = 0x18;
+ c = 1;
+ break;
+ case '*':
+ gv2(RC_INT, RC_INT);
+ r = vtop[-1].r;
+ fr = vtop[0].r;
+ vtop--;
+ o(0xE0000090 | (intr(r) << 16) | (intr(r) << 8) | intr(fr));
+ return;
+ case TOK_SHL:
+ opc = 0;
+ c = 2;
+ break;
+ case TOK_SHR:
+ opc = 1;
+ c = 2;
+ break;
+ case TOK_SAR:
+ opc = 2;
+ c = 2;
+ break;
+ case '/':
+ case TOK_PDIV:
+ func = TOK___divsi3;
+ c = 3;
+ break;
+ case TOK_UDIV:
+ func = TOK___udivsi3;
+ c = 3;
+ break;
+ case '%':
+#ifdef TCC_ARM_EABI
+ func = TOK___aeabi_idivmod;
+ retreg = REG_LRET;
+#else
+ func = TOK___modsi3;
+#endif
+ c = 3;
+ break;
+ case TOK_UMOD:
+#ifdef TCC_ARM_EABI
+ func = TOK___aeabi_uidivmod;
+ retreg = REG_LRET;
+#else
+ func = TOK___umodsi3;
+#endif
+ c = 3;
+ break;
+ case TOK_UMULL:
+ gv2(RC_INT, RC_INT);
+ r = intr(vtop[-1].r2 = get_reg(RC_INT));
+ c = vtop[-1].r;
+ vtop[-1].r = get_reg_ex(RC_INT, regmask(c));
+ vtop--;
+ o(0xE0800090 | (r << 16) | (intr(vtop->r) << 12) | (intr(c) << 8) |
+ intr(vtop[1].r));
+ return;
+ default:
+ opc = 0x15;
+ c = 1;
+ break;
+ }
+ switch (c) {
+ case 1:
+ if ((vtop[-1].r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
+ if (opc == 4 || opc == 5 || opc == 0xc) {
+ vswap();
+ opc |= 2; // sub -> rsb
+ }
+ }
+ if ((vtop->r & VT_VALMASK) == VT_CMP ||
+ (vtop->r & (VT_VALMASK & ~1)) == VT_JMP)
+ gv(RC_INT);
+ vswap();
+ c = intr(gv(RC_INT));
+ vswap();
+ opc = 0xE0000000 | (opc << 20) | (c << 16);
+ if ((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
+ uint32_t x;
+ x = stuff_const(opc | 0x2000000, vtop->c.i);
+ if (x) {
+ r = intr(vtop[-1].r = get_reg_ex(RC_INT, regmask(vtop[-1].r)));
+ o(x | (r << 12));
+ goto done;
+ }
+ }
+ fr = intr(gv(RC_INT));
+ r = intr(vtop[-1].r =
+ get_reg_ex(RC_INT, two2mask(vtop->r, vtop[-1].r)));
+ o(opc | (r << 12) | fr);
+ done:
+ vtop--;
+ if (op >= TOK_ULT && op <= TOK_GT) {
+ vtop->r = VT_CMP;
+ vtop->c.i = op;
+ }
+ break;
+ case 2:
+ opc = 0xE1A00000 | (opc << 5);
+ if ((vtop->r & VT_VALMASK) == VT_CMP ||
+ (vtop->r & (VT_VALMASK & ~1)) == VT_JMP)
+ gv(RC_INT);
+ vswap();
+ r = intr(gv(RC_INT));
+ vswap();
+ opc |= r;
+ if ((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
+ fr = intr(vtop[-1].r = get_reg_ex(RC_INT, regmask(vtop[-1].r)));
+ c = vtop->c.i & 0x1f;
+ o(opc | (c << 7) | (fr << 12));
+ } else {
+ fr = intr(gv(RC_INT));
+ c = intr(vtop[-1].r =
+ get_reg_ex(RC_INT, two2mask(vtop->r, vtop[-1].r)));
+ o(opc | (c << 12) | (fr << 8) | 0x10);
+ }
+ vtop--;
+ break;
+ case 3:
+ vpush_global_sym(&func_old_type, func);
+ vrott(3);
+ gfunc_call(2);
+ vpushi(0);
+ vtop->r = retreg;
+ break;
+ default:
+ tcc_error("gen_opi %i unimplemented!", op);
+ }
+}
+
+#ifdef TCC_ARM_VFP
+static int is_zero(int i)
+{
+ if ((vtop[i].r & (VT_VALMASK | VT_LVAL | VT_SYM)) != VT_CONST)
+ return 0;
+ if (vtop[i].type.t == VT_FLOAT)
+ return (vtop[i].c.f == 0.f);
+ else if (vtop[i].type.t == VT_DOUBLE)
+ return (vtop[i].c.d == 0.0);
+ return (vtop[i].c.ld == 0.l);
+}
+
+/* generate a floating point operation 'v = t1 op t2' instruction. The
+ * two operands are guaranted to have the same floating point type */
+void gen_opf(int op)
+{
+ uint32_t x;
+ int fneg = 0, r;
+ x = 0xEE000A00 | T2CPR(vtop->type.t);
+ switch (op) {
+ case '+':
+ if (is_zero(-1))
+ vswap();
+ if (is_zero(0)) {
+ vtop--;
+ return;
+ }
+ x |= 0x300000;
+ break;
+ case '-':
+ x |= 0x300040;
+ if (is_zero(0)) {
+ vtop--;
+ return;
+ }
+ if (is_zero(-1)) {
+ x |= 0x810000; /* fsubX -> fnegX */
+ vswap();
+ vtop--;
+ fneg = 1;
+ }
+ break;
+ case '*':
+ x |= 0x200000;
+ break;
+ case '/':
+ x |= 0x800000;
+ break;
+ default:
+ if (op < TOK_ULT || op > TOK_GT) {
+ tcc_error("unknown fp op %x!", op);
+ return;
+ }
+ if (is_zero(-1)) {
+ vswap();
+ switch(op) {
+ case TOK_LT: op = TOK_GT; break;
+ case TOK_GE: op = TOK_ULE; break;
+ case TOK_LE: op = TOK_GE; break;
+ case TOK_GT: op = TOK_ULT; break;
+ }
+ }
+ x |= 0xB40040; /* fcmpX */
+ if (op != TOK_EQ && op != TOK_NE)
+ x |= 0x80; /* fcmpX -> fcmpeX */
+ if (is_zero(0)) {
+ vtop--;
+ o(x | 0x10000 |
+ (vfpr(gv(RC_FLOAT)) << 12)); /* fcmp(e)X -> fcmp(e)zX */
+ } else {
+ x |= vfpr(gv(RC_FLOAT));
+ vswap();
+ o(x | (vfpr(gv(RC_FLOAT)) << 12));
+ vtop--;
+ }
+ o(0xEEF1FA10); /* fmstat */
+
+ switch(op) {
+ case TOK_LE: op = TOK_ULE; break;
+ case TOK_LT: op = TOK_ULT; break;
+ case TOK_UGE: op = TOK_GE; break;
+ case TOK_UGT: op = TOK_GT; break;
+ }
+
+ vtop->r = VT_CMP;
+ vtop->c.i = op;
+ return;
+ }
+ r = gv(RC_FLOAT);
+ x |= vfpr(r);
+ r = regmask(r);
+ if (!fneg) {
+ int r2;
+ vswap();
+ r2 = gv(RC_FLOAT);
+ x |= vfpr(r2) << 16;
+ r |= regmask(r2);
+ }
+ vtop->r = get_reg_ex(RC_FLOAT, r);
+ if (!fneg)
+ vtop--;
+ o(x | (vfpr(vtop->r) << 12));
+}
+
+#else
+static uint32_t is_fconst()
+{
+ long double f;
+ uint32_t r;
+ if ((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) != VT_CONST)
+ return 0;
+ if (vtop->type.t == VT_FLOAT)
+ f = vtop->c.f;
+ else if (vtop->type.t == VT_DOUBLE)
+ f = vtop->c.d;
+ else
+ f = vtop->c.ld;
+ if (!ieee_finite(f))
+ return 0;
+ r = 0x8;
+ if (f < 0.0) {
+ r = 0x18;
+ f = -f;
+ }
+ if (f == 0.0)
+ return r;
+ if (f == 1.0)
+ return r | 1;
+ if (f == 2.0)
+ return r | 2;
+ if (f == 3.0)
+ return r | 3;
+ if (f == 4.0)
+ return r | 4;
+ if (f == 5.0)
+ return r | 5;
+ if (f == 0.5)
+ return r | 6;
+ if (f == 10.0)
+ return r | 7;
+ return 0;
+}
+
+/* generate a floating point operation 'v = t1 op t2' instruction. The
+ two operands are guaranted to have the same floating point type */
+void gen_opf(int op)
+{
+ uint32_t x, r, r2, c1, c2;
+ // fputs("gen_opf\n",stderr);
+ vswap();
+ c1 = is_fconst();
+ vswap();
+ c2 = is_fconst();
+ x = 0xEE000100;
+#if LDOUBLE_SIZE == 8
+ if ((vtop->type.t & VT_BTYPE) != VT_FLOAT)
+ x |= 0x80;
+#else
+ if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE)
+ x |= 0x80;
+ else if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE)
+ x |= 0x80000;
+#endif
+ switch (op) {
+ case '+':
+ if (!c2) {
+ vswap();
+ c2 = c1;
+ }
+ vswap();
+ r = fpr(gv(RC_FLOAT));
+ vswap();
+ if (c2) {
+ if (c2 > 0xf)
+ x |= 0x200000; // suf
+ r2 = c2 & 0xf;
+ } else {
+ r2 = fpr(gv(RC_FLOAT));
+ }
+ break;
+ case '-':
+ if (c2) {
+ if (c2 <= 0xf)
+ x |= 0x200000; // suf
+ r2 = c2 & 0xf;
+ vswap();
+ r = fpr(gv(RC_FLOAT));
+ vswap();
+ } else if (c1 && c1 <= 0xf) {
+ x |= 0x300000; // rsf
+ r2 = c1;
+ r = fpr(gv(RC_FLOAT));
+ vswap();
+ } else {
+ x |= 0x200000; // suf
+ vswap();
+ r = fpr(gv(RC_FLOAT));
+ vswap();
+ r2 = fpr(gv(RC_FLOAT));
+ }
+ break;
+ case '*':
+ if (!c2 || c2 > 0xf) {
+ vswap();
+ c2 = c1;
+ }
+ vswap();
+ r = fpr(gv(RC_FLOAT));
+ vswap();
+ if (c2 && c2 <= 0xf)
+ r2 = c2;
+ else
+ r2 = fpr(gv(RC_FLOAT));
+ x |= 0x100000; // muf
+ break;
+ case '/':
+ if (c2 && c2 <= 0xf) {
+ x |= 0x400000; // dvf
+ r2 = c2;
+ vswap();
+ r = fpr(gv(RC_FLOAT));
+ vswap();
+ } else if (c1 && c1 <= 0xf) {
+ x |= 0x500000; // rdf
+ r2 = c1;
+ r = fpr(gv(RC_FLOAT));
+ vswap();
+ } else {
+ x |= 0x400000; // dvf
+ vswap();
+ r = fpr(gv(RC_FLOAT));
+ vswap();
+ r2 = fpr(gv(RC_FLOAT));
+ }
+ break;
+ default:
+ if (op >= TOK_ULT && op <= TOK_GT) {
+ x |= 0xd0f110; // cmfe
+ /* bug (intention?) in Linux FPU emulator
+ doesn't set carry if equal */
+ switch (op) {
+ case TOK_ULT:
+ case TOK_UGE:
+ case TOK_ULE:
+ case TOK_UGT:
+ tcc_error("unsigned comparison on floats?");
+ break;
+ case TOK_LT:
+ op = TOK_Nset;
+ break;
+ case TOK_LE:
+ op = TOK_ULE; /* correct in unordered case only if AC bit in
+ FPSR set */
+ break;
+ case TOK_EQ:
+ case TOK_NE:
+ x &= ~0x400000; // cmfe -> cmf
+ break;
+ }
+ if (c1 && !c2) {
+ c2 = c1;
+ vswap();
+ switch (op) {
+ case TOK_Nset:
+ op = TOK_GT;
+ break;
+ case TOK_GE:
+ op = TOK_ULE;
+ break;
+ case TOK_ULE:
+ op = TOK_GE;
+ break;
+ case TOK_GT:
+ op = TOK_Nset;
+ break;
+ }
+ }
+ vswap();
+ r = fpr(gv(RC_FLOAT));
+ vswap();
+ if (c2) {
+ if (c2 > 0xf)
+ x |= 0x200000;
+ r2 = c2 & 0xf;
+ } else {
+ r2 = fpr(gv(RC_FLOAT));
+ }
+ vtop[-1].r = VT_CMP;
+ vtop[-1].c.i = op;
+ } else {
+ tcc_error("unknown fp op %x!", op);
+ return;
+ }
+ }
+ if (vtop[-1].r == VT_CMP)
+ c1 = 15;
+ else {
+ c1 = vtop->r;
+ if (r2 & 0x8)
+ c1 = vtop[-1].r;
+ vtop[-1].r = get_reg_ex(RC_FLOAT, two2mask(vtop[-1].r, c1));
+ c1 = fpr(vtop[-1].r);
+ }
+ vtop--;
+ o(x | (r << 16) | (c1 << 12) | r2);
+}
+#endif
+
+/* convert integers to fp 't' type. Must handle 'int', 'unsigned int'
+ and 'long long' cases. */
+ST_FUNC void gen_cvt_itof1(int t)
+{
+ uint32_t r, r2;
+ int bt;
+ bt = vtop->type.t & VT_BTYPE;
+ if (bt == VT_INT || bt == VT_SHORT || bt == VT_BYTE) {
+#ifndef TCC_ARM_VFP
+ uint32_t dsize = 0;
+#endif
+ r = intr(gv(RC_INT));
+#ifdef TCC_ARM_VFP
+ r2 = vfpr(vtop->r = get_reg(RC_FLOAT));
+ o(0xEE000A10 | (r << 12) | (r2 << 16)); /* fmsr */
+ r2 |= r2 << 12;
+ if (!(vtop->type.t & VT_UNSIGNED))
+ r2 |= 0x80; /* fuitoX -> fsituX */
+ o(0xEEB80A40 | r2 | T2CPR(t)); /* fYitoX*/
+#else
+ r2 = fpr(vtop->r = get_reg(RC_FLOAT));
+ if ((t & VT_BTYPE) != VT_FLOAT)
+ dsize = 0x80; /* flts -> fltd */
+ o(0xEE000110 | dsize | (r2 << 16) | (r << 12)); /* flts */
+ if ((vtop->type.t & (VT_UNSIGNED | VT_BTYPE)) ==
+ (VT_UNSIGNED | VT_INT)) {
+ uint32_t off = 0;
+ o(0xE3500000 | (r << 12)); /* cmp */
+ r = fpr(get_reg(RC_FLOAT));
+ if (last_itod_magic) {
+ off = ind + 8 - last_itod_magic;
+ off /= 4;
+ if (off > 255)
+ off = 0;
+ }
+ o(0xBD1F0100 | (r << 12) | off); /* ldflts */
+ if (!off) {
+ o(0xEA000000); /* b */
+ last_itod_magic = ind;
+ o(0x4F800000); /* 4294967296.0f */
+ }
+ o(0xBE000100 | dsize | (r2 << 16) | (r2 << 12) | r); /* adflt */
+ }
+#endif
+ return;
+ } else if (bt == VT_LLONG) {
+ int func;
+ CType* func_type = 0;
+ if ((t & VT_BTYPE) == VT_FLOAT) {
+ func_type = &func_float_type;
+ if (vtop->type.t & VT_UNSIGNED)
+ func = TOK___floatundisf;
+ else
+ func = TOK___floatdisf;
+#if LDOUBLE_SIZE != 8
+ } else if ((t & VT_BTYPE) == VT_LDOUBLE) {
+ func_type = &func_ldouble_type;
+ if (vtop->type.t & VT_UNSIGNED)
+ func = TOK___floatundixf;
+ else
+ func = TOK___floatdixf;
+ } else if ((t & VT_BTYPE) == VT_DOUBLE) {
+#else
+ } else if ((t & VT_BTYPE) == VT_DOUBLE ||
+ (t & VT_BTYPE) == VT_LDOUBLE) {
+#endif
+ func_type = &func_double_type;
+ if (vtop->type.t & VT_UNSIGNED)
+ func = TOK___floatundidf;
+ else
+ func = TOK___floatdidf;
+ }
+ if (func_type) {
+ vpush_global_sym(func_type, func);
+ vswap();
+ gfunc_call(1);
+ vpushi(0);
+ vtop->r = TREG_F0;
+ return;
+ }
+ }
+ tcc_error("unimplemented gen_cvt_itof %x!", vtop->type.t);
+}
+
+/* convert fp to int 't' type */
+void gen_cvt_ftoi(int t)
+{
+ uint32_t r, r2;
+ int u, func = 0;
+ u = t & VT_UNSIGNED;
+ t &= VT_BTYPE;
+ r2 = vtop->type.t & VT_BTYPE;
+ if (t == VT_INT) {
+#ifdef TCC_ARM_VFP
+ r = vfpr(gv(RC_FLOAT));
+ u = u ? 0 : 0x10000;
+ o(0xEEBC0AC0 | (r << 12) | r | T2CPR(r2) | u); /* ftoXizY */
+ r2 = intr(vtop->r = get_reg(RC_INT));
+ o(0xEE100A10 | (r << 16) | (r2 << 12));
+ return;
+#else
+ if (u) {
+ if (r2 == VT_FLOAT)
+ func = TOK___fixunssfsi;
+#if LDOUBLE_SIZE != 8
+ else if (r2 == VT_LDOUBLE)
+ func = TOK___fixunsxfsi;
+ else if (r2 == VT_DOUBLE)
+#else
+ else if (r2 == VT_LDOUBLE || r2 == VT_DOUBLE)
+#endif
+ func = TOK___fixunsdfsi;
+ } else {
+ r = fpr(gv(RC_FLOAT));
+ r2 = intr(vtop->r = get_reg(RC_INT));
+ o(0xEE100170 | (r2 << 12) | r);
+ return;
+ }
+#endif
+ } else if (t == VT_LLONG) { // unsigned handled in gen_cvt_ftoi1
+ if (r2 == VT_FLOAT)
+ func = TOK___fixsfdi;
+#if LDOUBLE_SIZE != 8
+ else if (r2 == VT_LDOUBLE)
+ func = TOK___fixxfdi;
+ else if (r2 == VT_DOUBLE)
+#else
+ else if (r2 == VT_LDOUBLE || r2 == VT_DOUBLE)
+#endif
+ func = TOK___fixdfdi;
+ }
+ if (func) {
+ vpush_global_sym(&func_old_type, func);
+ vswap();
+ gfunc_call(1);
+ vpushi(0);
+ if (t == VT_LLONG)
+ vtop->r2 = REG_LRET;
+ vtop->r = REG_IRET;
+ return;
+ }
+ tcc_error("unimplemented gen_cvt_ftoi!");
+}
+
+/* convert from one floating point type to another */
+void gen_cvt_ftof(int t)
+{
+#ifdef TCC_ARM_VFP
+ if (((vtop->type.t & VT_BTYPE) == VT_FLOAT) !=
+ ((t & VT_BTYPE) == VT_FLOAT)) {
+ uint32_t r = vfpr(gv(RC_FLOAT));
+ o(0xEEB70AC0 | (r << 12) | r | T2CPR(vtop->type.t));
+ }
+#else
+ /* all we have to do on i386 and FPA ARM is to put the float in a register
+ */
+ gv(RC_FLOAT);
+#endif
+}
+
+/* computed goto support */
+void ggoto(void)
+{
+ gcall_or_jmp(1);
+ vtop--;
+}
+
+/* Save the stack pointer onto the stack and return the location of its address
+ */
+ST_FUNC void gen_vla_sp_save(int addr)
+{
+ tcc_error("variable length arrays unsupported for this target");
+}
+
+/* Restore the SP from a location on the stack */
+ST_FUNC void gen_vla_sp_restore(int addr)
+{
+ tcc_error("variable length arrays unsupported for this target");
+}
+
+/* Subtract from the stack pointer, and push the resulting value onto the stack
+ */
+ST_FUNC void gen_vla_alloc(CType* type, int align)
+{
+ tcc_error("variable length arrays unsupported for this target");
+}
+
+/* end of ARM code generator */
+/*************************************************************/
+#endif
+/*************************************************************/
diff --git a/src/arm/arm64-gen.c b/src/arm/arm64-gen.c
new file mode 100644
index 0000000..fe3d7aa
--- /dev/null
+++ b/src/arm/arm64-gen.c
@@ -0,0 +1,1846 @@
+/*
+ * A64 code generator for TCC
+ *
+ * Copyright (c) 2014-2015 Edmund Grimley Evans
+ *
+ * Copying and distribution of this file, with or without modification,
+ * are permitted in any medium without royalty provided the copyright
+ * notice and this notice are preserved. This file is offered as-is,
+ * without any warranty.
+ */
+
+#ifdef TARGET_DEFS_ONLY
+
+// Number of registers available to allocator:
+#define NB_REGS 28 // x0-x18, x30, v0-v7
+
+typedef int RegArgs;
+
+#define TREG_R(x) (x) // x = 0..18
+#define TREG_R30 19
+#define TREG_F(x) (x + 20) // x = 0..7
+
+// Register classes sorted from more general to more precise:
+#define RC_INT (1 << 0)
+#define RC_FLOAT (1 << 1)
+#define RC_R(x) (1 << (2 + (x))) // x = 0..18
+#define RC_R30 (1 << 21)
+#define RC_F(x) (1 << (22 + (x))) // x = 0..7
+
+#define RC_IRET (RC_R(0)) // int return register class
+#define RC_FRET (RC_F(0)) // float return register class
+
+#define REG_IRET (TREG_R(0)) // int return register number
+#define REG_FRET (TREG_F(0)) // float return register number
+
+#define PTR_SIZE 8
+
+#define LDOUBLE_SIZE 16
+#define LDOUBLE_ALIGN 16
+
+#define MAX_ALIGN 16
+
+#define CHAR_IS_UNSIGNED
+
+/******************************************************/
+/* ELF defines */
+
+#define EM_TCC_TARGET EM_AARCH64
+
+#define R_DATA_32 R_AARCH64_ABS32
+#define R_DATA_PTR R_AARCH64_ABS64
+#define R_JMP_SLOT R_AARCH64_JUMP_SLOT
+#define R_COPY R_AARCH64_COPY
+
+#define ELF_START_ADDR 0x00400000
+#define ELF_PAGE_SIZE 0x1000
+
+/******************************************************/
+#else /* ! TARGET_DEFS_ONLY */
+/******************************************************/
+#include "../tcc.h"
+#include <assert.h>
+
+ST_DATA const int reg_classes[NB_REGS] = {
+ RC_INT | RC_R(0),
+ RC_INT | RC_R(1),
+ RC_INT | RC_R(2),
+ RC_INT | RC_R(3),
+ RC_INT | RC_R(4),
+ RC_INT | RC_R(5),
+ RC_INT | RC_R(6),
+ RC_INT | RC_R(7),
+ RC_INT | RC_R(8),
+ RC_INT | RC_R(9),
+ RC_INT | RC_R(10),
+ RC_INT | RC_R(11),
+ RC_INT | RC_R(12),
+ RC_INT | RC_R(13),
+ RC_INT | RC_R(14),
+ RC_INT | RC_R(15),
+ RC_INT | RC_R(16),
+ RC_INT | RC_R(17),
+ RC_INT | RC_R(18),
+ RC_R30, // not in RC_INT as we make special use of x30
+ RC_FLOAT | RC_F(0),
+ RC_FLOAT | RC_F(1),
+ RC_FLOAT | RC_F(2),
+ RC_FLOAT | RC_F(3),
+ RC_FLOAT | RC_F(4),
+ RC_FLOAT | RC_F(5),
+ RC_FLOAT | RC_F(6),
+ RC_FLOAT | RC_F(7)
+};
+
+#define IS_FREG(x) ((x) >= TREG_F(0))
+
+static uint32_t intr(int r)
+{
+ assert(TREG_R(0) <= r && r <= TREG_R30);
+ return r < TREG_R30 ? r : 30;
+}
+
+static uint32_t fltr(int r)
+{
+ assert(TREG_F(0) <= r && r <= TREG_F(7));
+ return r - TREG_F(0);
+}
+
+// Add an instruction to text section:
+ST_FUNC void o(unsigned int c)
+{
+ int ind1 = ind + 4;
+ if (ind1 > cur_text_section->data_allocated)
+ section_realloc(cur_text_section, ind1);
+ *(uint32_t *)(cur_text_section->data + ind) = c;
+ ind = ind1;
+}
+
+static int arm64_encode_bimm64(uint64_t x)
+{
+ int neg = x & 1;
+ int rep, pos, len;
+
+ if (neg)
+ x = ~x;
+ if (!x)
+ return -1;
+
+ if (x >> 2 == (x & (((uint64_t)1 << (64 - 2)) - 1)))
+ rep = 2, x &= ((uint64_t)1 << 2) - 1;
+ else if (x >> 4 == (x & (((uint64_t)1 << (64 - 4)) - 1)))
+ rep = 4, x &= ((uint64_t)1 << 4) - 1;
+ else if (x >> 8 == (x & (((uint64_t)1 << (64 - 8)) - 1)))
+ rep = 8, x &= ((uint64_t)1 << 8) - 1;
+ else if (x >> 16 == (x & (((uint64_t)1 << (64 - 16)) - 1)))
+ rep = 16, x &= ((uint64_t)1 << 16) - 1;
+ else if (x >> 32 == (x & (((uint64_t)1 << (64 - 32)) - 1)))
+ rep = 32, x &= ((uint64_t)1 << 32) - 1;
+ else
+ rep = 64;
+
+ pos = 0;
+ if (!(x & (((uint64_t)1 << 32) - 1))) x >>= 32, pos += 32;
+ if (!(x & (((uint64_t)1 << 16) - 1))) x >>= 16, pos += 16;
+ if (!(x & (((uint64_t)1 << 8) - 1))) x >>= 8, pos += 8;
+ if (!(x & (((uint64_t)1 << 4) - 1))) x >>= 4, pos += 4;
+ if (!(x & (((uint64_t)1 << 2) - 1))) x >>= 2, pos += 2;
+ if (!(x & (((uint64_t)1 << 1) - 1))) x >>= 1, pos += 1;
+
+ len = 0;
+ if (!(~x & (((uint64_t)1 << 32) - 1))) x >>= 32, len += 32;
+ if (!(~x & (((uint64_t)1 << 16) - 1))) x >>= 16, len += 16;
+ if (!(~x & (((uint64_t)1 << 8) - 1))) x >>= 8, len += 8;
+ if (!(~x & (((uint64_t)1 << 4) - 1))) x >>= 4, len += 4;
+ if (!(~x & (((uint64_t)1 << 2) - 1))) x >>= 2, len += 2;
+ if (!(~x & (((uint64_t)1 << 1) - 1))) x >>= 1, len += 1;
+
+ if (x)
+ return -1;
+ if (neg) {
+ pos = (pos + len) & (rep - 1);
+ len = rep - len;
+ }
+ return ((0x1000 & rep << 6) | (((rep - 1) ^ 31) << 1 & 63) |
+ ((rep - pos) & (rep - 1)) << 6 | (len - 1));
+}
+
+static uint32_t arm64_movi(int r, uint64_t x)
+{
+ uint64_t m = 0xffff;
+ int e;
+ if (!(x & ~m))
+ return 0x52800000 | r | x << 5; // movz w(r),#(x)
+ if (!(x & ~(m << 16)))
+ return 0x52a00000 | r | x >> 11; // movz w(r),#(x >> 16),lsl #16
+ if (!(x & ~(m << 32)))
+ return 0xd2c00000 | r | x >> 27; // movz x(r),#(x >> 32),lsl #32
+ if (!(x & ~(m << 48)))
+ return 0xd2e00000 | r | x >> 43; // movz x(r),#(x >> 48),lsl #48
+ if ((x & ~m) == m << 16)
+ return (0x12800000 | r |
+ (~x << 5 & 0x1fffe0)); // movn w(r),#(~x)
+ if ((x & ~(m << 16)) == m)
+ return (0x12a00000 | r |
+ (~x >> 11 & 0x1fffe0)); // movn w(r),#(~x >> 16),lsl #16
+ if (!~(x | m))
+ return (0x92800000 | r |
+ (~x << 5 & 0x1fffe0)); // movn x(r),#(~x)
+ if (!~(x | m << 16))
+ return (0x92a00000 | r |
+ (~x >> 11 & 0x1fffe0)); // movn x(r),#(~x >> 16),lsl #16
+ if (!~(x | m << 32))
+ return (0x92c00000 | r |
+ (~x >> 27 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
+ if (!~(x | m << 48))
+ return (0x92e00000 | r |
+ (~x >> 43 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
+ if (!(x >> 32) && (e = arm64_encode_bimm64(x | x << 32)) >= 0)
+ return 0x320003e0 | r | (uint32_t)e << 10; // movi w(r),#(x)
+ if ((e = arm64_encode_bimm64(x)) >= 0)
+ return 0xb20003e0 | r | (uint32_t)e << 10; // movi x(r),#(x)
+ return 0;
+}
+
+static void arm64_movimm(int r, uint64_t x)
+{
+ uint32_t i;
+ if ((i = arm64_movi(r, x)))
+ o(i); // a single MOV
+ else {
+ // MOVZ/MOVN and 1-3 MOVKs
+ int z = 0, m = 0;
+ uint32_t mov1 = 0xd2800000; // movz
+ uint64_t x1 = x;
+ for (i = 0; i < 64; i += 16) {
+ z += !(x >> i & 0xffff);
+ m += !(~x >> i & 0xffff);
+ }
+ if (m > z) {
+ x1 = ~x;
+ mov1 = 0x92800000; // movn
+ }
+ for (i = 0; i < 64; i += 16)
+ if (x1 >> i & 0xffff) {
+ o(mov1 | r | (x1 >> i & 0xffff) << 5 | i << 17);
+ // movz/movn x(r),#(*),lsl #(i)
+ break;
+ }
+ for (i += 16; i < 64; i += 16)
+ if (x1 >> i & 0xffff)
+ o(0xf2800000 | r | (x >> i & 0xffff) << 5 | i << 17);
+ // movk x(r),#(*),lsl #(i)
+ }
+}
+
+// Patch all branches in list pointed to by t to branch to a:
+ST_FUNC void gsym_addr(int t_, int a_)
+{
+ uint32_t t = t_;
+ uint32_t a = a_;
+ while (t) {
+ uint32_t *ptr = (uint32_t *)(cur_text_section->data + t);
+ uint32_t next = *ptr;
+ if (a - t + 0x8000000 >= 0x10000000)
+ tcc_error("branch out of range");
+ *ptr = (a - t == 4 ? 0xd503201f : // nop
+ 0x14000000 | ((a - t) >> 2 & 0x3ffffff)); // b
+ t = next;
+ }
+}
+
+// Patch all branches in list pointed to by t to branch to current location:
+ST_FUNC void gsym(int t)
+{
+ gsym_addr(t, ind);
+}
+
+static int arm64_type_size(int t)
+{
+ switch (t & VT_BTYPE) {
+ case VT_INT: return 2;
+ case VT_BYTE: return 0;
+ case VT_SHORT: return 1;
+ case VT_PTR: return 3;
+ case VT_ENUM: return 2;
+ case VT_FUNC: return 3;
+ case VT_FLOAT: return 2;
+ case VT_DOUBLE: return 3;
+ case VT_LDOUBLE: return 4;
+ case VT_BOOL: return 0;
+ case VT_LLONG: return 3;
+ }
+ assert(0);
+ return 0;
+}
+
+static void arm64_spoff(int reg, uint64_t off)
+{
+ uint32_t sub = off >> 63;
+ if (sub)
+ off = -off;
+ if (off < 4096)
+ o(0x910003e0 | sub << 30 | reg | off << 10);
+ // (add|sub) x(reg),sp,#(off)
+ else {
+ arm64_movimm(30, off); // use x30 for offset
+ o(0x8b3e63e0 | sub << 30 | reg); // (add|sub) x(reg),sp,x30
+ }
+}
+
+static void arm64_ldrx(int sg, int sz, int dst, int bas, uint64_t off)
+{
+ if (sz >= 2)
+ sg = 0;
+ if (!(off & ~(0xfff << sz)))
+ o(0x39400000 | dst | bas << 5 | off << (10 - sz) |
+ !!sg << 23 | sz << 30); // ldr(*) x(dst),[x(bas),#(off)]
+ else if (off < 256 || -off <= 256)
+ o(0x38400000 | dst | bas << 5 | (off & 511) << 12 |
+ !!sg << 23 | sz << 30); // ldur(*) x(dst),[x(bas),#(off)]
+ else {
+ arm64_movimm(30, off); // use x30 for offset
+ o(0x38206800 | dst | bas << 5 | 30 << 16 |
+ (!!sg + 1) << 22 | sz << 30); // ldr(*) x(dst),[x(bas),x30]
+ }
+}
+
+static void arm64_ldrv(int sz, int dst, int bas, uint64_t off)
+{
+ if (!(off & ~(0xfff << sz)))
+ o(0x3d400000 | dst | bas << 5 | off << (10 - sz) |
+ (sz & 4) << 21 | (sz & 3) << 30); // ldr (s|d|q)(dst),[x(bas),#(off)]
+ else if (off < 256 || -off <= 256)
+ o(0x3c400000 | dst | bas << 5 | (off & 511) << 12 |
+ (sz & 4) << 21 | (sz & 3) << 30); // ldur (s|d|q)(dst),[x(bas),#(off)]
+ else {
+ arm64_movimm(30, off); // use x30 for offset
+ o(0x3c606800 | dst | bas << 5 | 30 << 16 | sz << 30 | (sz & 4) << 21);
+ // ldr (s|d|q)(dst),[x(bas),x30]
+ }
+}
+
+static void arm64_ldrs(int reg, int size)
+{
+ // Use x30 for intermediate value in some cases.
+ switch (size) {
+ default: assert(0); break;
+ case 1:
+ arm64_ldrx(0, 0, reg, reg, 0);
+ break;
+ case 2:
+ arm64_ldrx(0, 1, reg, reg, 0);
+ break;
+ case 3:
+ arm64_ldrx(0, 1, 30, reg, 0);
+ arm64_ldrx(0, 0, reg, reg, 2);
+ o(0x2a0043c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #16
+ break;
+ case 4:
+ arm64_ldrx(0, 2, reg, reg, 0);
+ break;
+ case 5:
+ arm64_ldrx(0, 2, 30, reg, 0);
+ arm64_ldrx(0, 0, reg, reg, 4);
+ o(0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
+ break;
+ case 6:
+ arm64_ldrx(0, 2, 30, reg, 0);
+ arm64_ldrx(0, 1, reg, reg, 4);
+ o(0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
+ break;
+ case 7:
+ arm64_ldrx(0, 2, 30, reg, 0);
+ arm64_ldrx(0, 2, reg, reg, 3);
+ o(0x53087c00 | reg | reg << 5); // lsr w(reg), w(reg), #8
+ o(0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
+ break;
+ case 8:
+ arm64_ldrx(0, 3, reg, reg, 0);
+ break;
+ case 9:
+ arm64_ldrx(0, 0, reg + 1, reg, 8);
+ arm64_ldrx(0, 3, reg, reg, 0);
+ break;
+ case 10:
+ arm64_ldrx(0, 1, reg + 1, reg, 8);
+ arm64_ldrx(0, 3, reg, reg, 0);
+ break;
+ case 11:
+ arm64_ldrx(0, 2, reg + 1, reg, 7);
+ o(0x53087c00 | (reg+1) | (reg+1) << 5); // lsr w(reg+1), w(reg+1), #8
+ arm64_ldrx(0, 3, reg, reg, 0);
+ break;
+ case 12:
+ arm64_ldrx(0, 2, reg + 1, reg, 8);
+ arm64_ldrx(0, 3, reg, reg, 0);
+ break;
+ case 13:
+ arm64_ldrx(0, 3, reg + 1, reg, 5);
+ o(0xd358fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #24
+ arm64_ldrx(0, 3, reg, reg, 0);
+ break;
+ case 14:
+ arm64_ldrx(0, 3, reg + 1, reg, 6);
+ o(0xd350fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #16
+ arm64_ldrx(0, 3, reg, reg, 0);
+ break;
+ case 15:
+ arm64_ldrx(0, 3, reg + 1, reg, 7);
+ o(0xd348fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #8
+ arm64_ldrx(0, 3, reg, reg, 0);
+ break;
+ case 16:
+ o(0xa9400000 | reg | (reg+1) << 10 | reg << 5);
+ // ldp x(reg),x(reg+1),[x(reg)]
+ break;
+ }
+}
+
+static void arm64_strx(int sz, int dst, int bas, uint64_t off)
+{
+ if (!(off & ~(0xfff << sz)))
+ o(0x39000000 | dst | bas << 5 | off << (10 - sz) | sz << 30);
+ // str(*) x(dst),[x(bas],#(off)]
+ else if (off < 256 || -off <= 256)
+ o(0x38000000 | dst | bas << 5 | (off & 511) << 12 | sz << 30);
+ // stur(*) x(dst),[x(bas],#(off)]
+ else {
+ arm64_movimm(30, off); // use x30 for offset
+ o(0x38206800 | dst | bas << 5 | 30 << 16 | sz << 30);
+ // str(*) x(dst),[x(bas),x30]
+ }
+}
+
+static void arm64_strv(int sz, int dst, int bas, uint64_t off)
+{
+ if (!(off & ~(0xfff << sz)))
+ o(0x3d000000 | dst | bas << 5 | off << (10 - sz) |
+ (sz & 4) << 21 | (sz & 3) << 30); // str (s|d|q)(dst),[x(bas),#(off)]
+ else if (off < 256 || -off <= 256)
+ o(0x3c000000 | dst | bas << 5 | (off & 511) << 12 |
+ (sz & 4) << 21 | (sz & 3) << 30); // stur (s|d|q)(dst),[x(bas),#(off)]
+ else {
+ arm64_movimm(30, off); // use x30 for offset
+ o(0x3c206800 | dst | bas << 5 | 30 << 16 | sz << 30 | (sz & 4) << 21);
+ // str (s|d|q)(dst),[x(bas),x30]
+ }
+}
+
+static void arm64_sym(int r, Sym *sym, unsigned long addend)
+{
+ // Currently TCC's linker does not generate COPY relocations for
+ // STT_OBJECTs when tcc is invoked with "-run". This typically
+ // results in "R_AARCH64_ADR_PREL_PG_HI21 relocation failed" when
+ // a program refers to stdin. A workaround is to avoid that
+ // relocation and use only relocations with unlimited range.
+ int avoid_adrp = 1;
+
+ if (avoid_adrp || (sym->type.t & VT_WEAK)) {
+ // (GCC uses a R_AARCH64_ABS64 in this case.)
+ greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G0_NC, addend);
+ o(0xd2800000 | r); // mov x(rt),#0,lsl #0
+ greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G1_NC, addend);
+ o(0xf2a00000 | r); // movk x(rt),#0,lsl #16
+ greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G2_NC, addend);
+ o(0xf2c00000 | r); // movk x(rt),#0,lsl #32
+ greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G3, addend);
+ o(0xf2e00000 | r); // movk x(rt),#0,lsl #48
+ }
+ else {
+ greloca(cur_text_section, sym, ind, R_AARCH64_ADR_PREL_PG_HI21, addend);
+ o(0x90000000 | r);
+ greloca(cur_text_section, sym, ind, R_AARCH64_ADD_ABS_LO12_NC, addend);
+ o(0x91000000 | r | r << 5);
+ }
+}
+
+ST_FUNC void load(int r, SValue *sv)
+{
+ int svtt = sv->type.t;
+ int svr = sv->r & ~VT_LVAL_TYPE;
+ int svrv = svr & VT_VALMASK;
+ uint64_t svcul = (int32_t)sv->c.ul;
+
+ if (svr == (VT_LOCAL | VT_LVAL)) {
+ if (IS_FREG(r))
+ arm64_ldrv(arm64_type_size(svtt), fltr(r), 29, svcul);
+ else
+ arm64_ldrx(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
+ intr(r), 29, svcul);
+ return;
+ }
+
+ if ((svr & ~VT_VALMASK) == VT_LVAL && svrv < VT_CONST) {
+ if (IS_FREG(r))
+ arm64_ldrv(arm64_type_size(svtt), fltr(r), intr(svrv), 0);
+ else
+ arm64_ldrx(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
+ intr(r), intr(svrv), 0);
+ return;
+ }
+
+ if (svr == (VT_CONST | VT_LVAL | VT_SYM)) {
+ arm64_sym(30, sv->sym, svcul); // use x30 for address
+ if (IS_FREG(r))
+ arm64_ldrv(arm64_type_size(svtt), fltr(r), 30, 0);
+ else
+ arm64_ldrx(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
+ intr(r), 30, 0);
+ return;
+ }
+
+ if (svr == (VT_CONST | VT_SYM)) {
+ arm64_sym(intr(r), sv->sym, svcul);
+ return;
+ }
+
+ if (svr == VT_CONST) {
+ if ((svtt & VT_BTYPE) != VT_VOID)
+ arm64_movimm(intr(r), arm64_type_size(svtt) == 3 ?
+ sv->c.ull : (uint32_t)svcul);
+ return;
+ }
+
+ if (svr < VT_CONST) {
+ if (IS_FREG(r) && IS_FREG(svr))
+ if (svtt == VT_LDOUBLE)
+ o(0x4ea01c00 | fltr(r) | fltr(svr) << 5);
+ // mov v(r).16b,v(svr).16b
+ else
+ o(0x1e604000 | fltr(r) | fltr(svr) << 5); // fmov d(r),d(svr)
+ else if (!IS_FREG(r) && !IS_FREG(svr))
+ o(0xaa0003e0 | intr(r) | intr(svr) << 16); // mov x(r),x(svr)
+ else
+ assert(0);
+ return;
+ }
+
+ if (svr == VT_LOCAL) {
+ if (-svcul < 0x1000)
+ o(0xd10003a0 | intr(r) | -svcul << 10); // sub x(r),x29,#...
+ else {
+ arm64_movimm(30, -svcul); // use x30 for offset
+ o(0xcb0003a0 | intr(r) | 30 << 16); // sub x(r),x29,x30
+ }
+ return;
+ }
+
+ if (svr == VT_JMP || svr == VT_JMPI) {
+ int t = (svr == VT_JMPI);
+ arm64_movimm(intr(r), t);
+ o(0x14000002); // b .+8
+ gsym(svcul);
+ arm64_movimm(intr(r), t ^ 1);
+ return;
+ }
+
+ if (svr == (VT_LLOCAL | VT_LVAL)) {
+ arm64_ldrx(0, 3, 30, 29, svcul); // use x30 for offset
+ if (IS_FREG(r))
+ arm64_ldrv(arm64_type_size(svtt), fltr(r), 30, 0);
+ else
+ arm64_ldrx(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
+ intr(r), 30, 0);
+ return;
+ }
+
+ printf("load(%x, (%x, %x, %llx))\n", r, svtt, sv->r, (long long)svcul);
+ assert(0);
+}
+
+ST_FUNC void store(int r, SValue *sv)
+{
+ int svtt = sv->type.t;
+ int svr = sv->r & ~VT_LVAL_TYPE;
+ int svrv = svr & VT_VALMASK;
+ uint64_t svcul = (int32_t)sv->c.ul;
+
+ if (svr == (VT_LOCAL | VT_LVAL)) {
+ if (IS_FREG(r))
+ arm64_strv(arm64_type_size(svtt), fltr(r), 29, svcul);
+ else
+ arm64_strx(arm64_type_size(svtt), intr(r), 29, svcul);
+ return;
+ }
+
+ if ((svr & ~VT_VALMASK) == VT_LVAL && svrv < VT_CONST) {
+ if (IS_FREG(r))
+ arm64_strv(arm64_type_size(svtt), fltr(r), intr(svrv), 0);
+ else
+ arm64_strx(arm64_type_size(svtt), intr(r), intr(svrv), 0);
+ return;
+ }
+
+ if (svr == (VT_CONST | VT_LVAL | VT_SYM)) {
+ arm64_sym(30, sv->sym, svcul); // use x30 for address
+ if (IS_FREG(r))
+ arm64_strv(arm64_type_size(svtt), fltr(r), 30, 0);
+ else
+ arm64_strx(arm64_type_size(svtt), intr(r), 30, 0);
+ return;
+ }
+
+ printf("store(%x, (%x, %x, %llx))\n", r, svtt, sv->r, (long long)svcul);
+ assert(0);
+}
+
+static void arm64_gen_bl_or_b(int b)
+{
+ if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
+ assert(!b);
+ if (vtop->r & VT_SYM)
+ greloc(cur_text_section, vtop->sym, ind, R_AARCH64_CALL26);
+ else
+ assert(0);
+ o(0x94000000); // bl .
+ }
+ else
+ o(0xd61f0000 | !b << 21 | intr(gv(RC_R30)) << 5); // br/blr
+}
+
+static int arm64_hfa_aux(CType *type, int *fsize, int num)
+{
+ if (is_float(type->t)) {
+ int a, n = type_size(type, &a);
+ if (num >= 4 || (*fsize && *fsize != n))
+ return -1;
+ *fsize = n;
+ return num + 1;
+ }
+ else if ((type->t & VT_BTYPE) == VT_STRUCT) {
+ int is_struct = 0; // rather than union
+ Sym *field;
+ for (field = type->ref->next; field; field = field->next)
+ if (field->c) {
+ is_struct = 1;
+ break;
+ }
+ if (is_struct) {
+ int num0 = num;
+ for (field = type->ref->next; field; field = field->next) {
+ if (field->c != (num - num0) * *fsize)
+ return -1;
+ num = arm64_hfa_aux(&field->type, fsize, num);
+ if (num == -1)
+ return -1;
+ }
+ if (type->ref->c != (num - num0) * *fsize)
+ return -1;
+ return num;
+ }
+ else { // union
+ int num0 = num;
+ for (field = type->ref->next; field; field = field->next) {
+ int num1 = arm64_hfa_aux(&field->type, fsize, num0);
+ if (num1 == -1)
+ return -1;
+ num = num1 < num ? num : num1;
+ }
+ if (type->ref->c != (num - num0) * *fsize)
+ return -1;
+ return num;
+ }
+ }
+ else if (type->t & VT_ARRAY) {
+ int num1;
+ if (!type->ref->c)
+ return num;
+ num1 = arm64_hfa_aux(&type->ref->type, fsize, num);
+ if (num1 == -1 || (num1 != num && type->ref->c > 4))
+ return -1;
+ num1 = num + type->ref->c * (num1 - num);
+ if (num1 > 4)
+ return -1;
+ return num1;
+ }
+ return -1;
+}
+
+static int arm64_hfa(CType *type, int *fsize)
+{
+ if ((type->t & VT_BTYPE) == VT_STRUCT || (type->t & VT_ARRAY)) {
+ int sz = 0;
+ int n = arm64_hfa_aux(type, &sz, 0);
+ if (0 < n && n <= 4) {
+ if (fsize)
+ *fsize = sz;
+ return n;
+ }
+ }
+ return 0;
+}
+
+static unsigned long arm64_pcs_aux(int n, CType **type, unsigned long *a)
+{
+ int nx = 0; // next integer register
+ int nv = 0; // next vector register
+ unsigned long ns = 32; // next stack offset
+ int i;
+
+ for (i = 0; i < n; i++) {
+ int hfa = arm64_hfa(type[i], 0);
+ int size, align;
+
+ if ((type[i]->t & VT_ARRAY) ||
+ (type[i]->t & VT_BTYPE) == VT_FUNC)
+ size = align = 8;
+ else
+ size = type_size(type[i], &align);
+
+ if (hfa)
+ // B.2
+ ;
+ else if (size > 16) {
+ // B.3: replace with pointer
+ if (nx < 8)
+ a[i] = nx++ << 1 | 1;
+ else {
+ ns = (ns + 7) & ~7;
+ a[i] = ns | 1;
+ ns += 8;
+ }
+ continue;
+ }
+ else if ((type[i]->t & VT_BTYPE) == VT_STRUCT)
+ // B.4
+ size = (size + 7) & ~7;
+
+ // C.1
+ if (is_float(type[i]->t) && nv < 8) {
+ a[i] = 16 + (nv++ << 1);
+ continue;
+ }
+
+ // C.2
+ if (hfa && nv + hfa <= 8) {
+ a[i] = 16 + (nv << 1);
+ nv += hfa;
+ continue;
+ }
+
+ // C.3
+ if (hfa) {
+ nv = 8;
+ size = (size + 7) & ~7;
+ }
+
+ // C.4
+ if (hfa || (type[i]->t & VT_BTYPE) == VT_LDOUBLE) {
+ ns = (ns + 7) & ~7;
+ ns = (ns + align - 1) & -align;
+ }
+
+ // C.5
+ if ((type[i]->t & VT_BTYPE) == VT_FLOAT)
+ size = 8;
+
+ // C.6
+ if (hfa || is_float(type[i]->t)) {
+ a[i] = ns;
+ ns += size;
+ continue;
+ }
+
+ // C.7
+ if ((type[i]->t & VT_BTYPE) != VT_STRUCT && size <= 8 && nx < 8) {
+ a[i] = nx++ << 1;
+ continue;
+ }
+
+ // C.8
+ if (align == 16)
+ nx = (nx + 1) & ~1;
+
+ // C.9
+ if ((type[i]->t & VT_BTYPE) != VT_STRUCT && size == 16 && nx < 7) {
+ a[i] = nx << 1;
+ nx += 2;
+ continue;
+ }
+
+ // C.10
+ if ((type[i]->t & VT_BTYPE) == VT_STRUCT && size <= (8 - nx) * 8) {
+ a[i] = nx << 1;
+ nx += (size + 7) >> 3;
+ continue;
+ }
+
+ // C.11
+ nx = 8;
+
+ // C.12
+ ns = (ns + 7) & ~7;
+ ns = (ns + align - 1) & -align;
+
+ // C.13
+ if ((type[i]->t & VT_BTYPE) == VT_STRUCT) {
+ a[i] = ns;
+ ns += size;
+ continue;
+ }
+
+ // C.14
+ if (size < 8)
+ size = 8;
+
+ // C.15
+ a[i] = ns;
+ ns += size;
+ }
+
+ return ns - 32;
+}
+
+static unsigned long arm64_pcs(int n, CType **type, unsigned long *a)
+{
+ unsigned long stack;
+
+ // Return type:
+ if ((type[0]->t & VT_BTYPE) == VT_VOID)
+ a[0] = -1;
+ else {
+ arm64_pcs_aux(1, type, a);
+ assert(a[0] == 0 || a[0] == 1 || a[0] == 16);
+ }
+
+ // Argument types:
+ stack = arm64_pcs_aux(n, type + 1, a + 1);
+
+ if (0) {
+ int i;
+ for (i = 0; i <= n; i++) {
+ if (!i)
+ printf("arm64_pcs return: ");
+ else
+ printf("arm64_pcs arg %d: ", i);
+ if (a[i] == (unsigned long)-1)
+ printf("void\n");
+ else if (a[i] == 1 && !i)
+ printf("X8 pointer\n");
+ else if (a[i] < 16)
+ printf("X%lu%s\n", a[i] / 2, a[i] & 1 ? " pointer" : "");
+ else if (a[i] < 32)
+ printf("V%lu\n", a[i] / 2 - 8);
+ else
+ printf("stack %lu%s\n",
+ (a[i] - 32) & ~1, a[i] & 1 ? " pointer" : "");
+ }
+ }
+
+ return stack;
+}
+
+ST_FUNC void gfunc_call(int nb_args)
+{
+ CType *return_type;
+ CType **t;
+ unsigned long *a, *a1;
+ unsigned long stack;
+ int i;
+
+ return_type = &vtop[-nb_args].type.ref->type;
+ if ((return_type->t & VT_BTYPE) == VT_STRUCT)
+ --nb_args;
+
+ t = tcc_malloc((nb_args + 1) * sizeof(*t));
+ a = tcc_malloc((nb_args + 1) * sizeof(*a));
+ a1 = tcc_malloc((nb_args + 1) * sizeof(*a1));
+
+ t[0] = return_type;
+ for (i = 0; i < nb_args; i++)
+ t[nb_args - i] = &vtop[-i].type;
+
+ stack = arm64_pcs(nb_args, t, a);
+
+ // Allocate space for structs replaced by pointer:
+ for (i = nb_args; i; i--)
+ if (a[i] & 1) {
+ SValue *arg = &vtop[i - nb_args];
+ int align, size = type_size(&arg->type, &align);
+ assert((arg->type.t & VT_BTYPE) == VT_STRUCT);
+ stack = (stack + align - 1) & -align;
+ a1[i] = stack;
+ stack += size;
+ }
+
+ stack = (stack + 15) >> 4 << 4;
+
+ assert(stack < 0x1000);
+ if (stack)
+ o(0xd10003ff | stack << 10); // sub sp,sp,#(n)
+
+ // First pass: set all values on stack
+ for (i = nb_args; i; i--) {
+ vpushv(vtop - nb_args + i);
+
+ if (a[i] & 1) {
+ // struct replaced by pointer
+ int r = get_reg(RC_INT);
+ arm64_spoff(intr(r), a1[i]);
+ vset(&vtop->type, r | VT_LVAL, 0);
+ vswap();
+ vstore();
+ if (a[i] >= 32) {
+ // pointer on stack
+ r = get_reg(RC_INT);
+ arm64_spoff(intr(r), a1[i]);
+ arm64_strx(3, intr(r), 31, (a[i] - 32) >> 1 << 1);
+ }
+ }
+ else if (a[i] >= 32) {
+ // value on stack
+ if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
+ int r = get_reg(RC_INT);
+ arm64_spoff(intr(r), a[i] - 32);
+ vset(&vtop->type, r | VT_LVAL, 0);
+ vswap();
+ vstore();
+ }
+ else if (is_float(vtop->type.t)) {
+ gv(RC_FLOAT);
+ arm64_strv(arm64_type_size(vtop[0].type.t),
+ fltr(vtop[0].r), 31, a[i] - 32);
+ }
+ else {
+ gv(RC_INT);
+ arm64_strx(arm64_type_size(vtop[0].type.t),
+ intr(vtop[0].r), 31, a[i] - 32);
+ }
+ }
+
+ --vtop;
+ }
+
+ // Second pass: assign values to registers
+ for (i = nb_args; i; i--, vtop--) {
+ if (a[i] < 16 && !(a[i] & 1)) {
+ // value in general-purpose registers
+ if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
+ int align, size = type_size(&vtop->type, &align);
+ vtop->type.t = VT_PTR;
+ gaddrof();
+ gv(RC_R(a[i] / 2));
+ arm64_ldrs(a[i] / 2, size);
+ }
+ else
+ gv(RC_R(a[i] / 2));
+ }
+ else if (a[i] < 16)
+ // struct replaced by pointer in register
+ arm64_spoff(a[i] / 2, a1[i]);
+ else if (a[i] < 32) {
+ // value in floating-point registers
+ if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
+ int j, sz, n = arm64_hfa(&vtop->type, &sz);
+ vtop->type.t = VT_PTR;
+ gaddrof();
+ gv(RC_R30);
+ for (j = 0; j < n; j++)
+ o(0x3d4003c0 |
+ (sz & 16) << 19 | -(sz & 8) << 27 | (sz & 4) << 29 |
+ (a[i] / 2 - 8 + j) |
+ j << 10); // ldr ([sdq])(*),[x30,#(j * sz)]
+ }
+ else
+ gv(RC_F(a[i] / 2 - 8));
+ }
+ }
+
+ if ((return_type->t & VT_BTYPE) == VT_STRUCT) {
+ if (a[0] == 1) {
+ // indirect return: set x8 and discard the stack value
+ gv(RC_R(8));
+ --vtop;
+ }
+ else
+ // return in registers: keep the address for after the call
+ vswap();
+ }
+
+ save_regs(0);
+ arm64_gen_bl_or_b(0);
+ --vtop;
+ if (stack)
+ o(0x910003ff | stack << 10); // add sp,sp,#(n)
+
+ {
+ int rt = return_type->t;
+ int bt = rt & VT_BTYPE;
+ if (bt == VT_BYTE || bt == VT_SHORT)
+ // Promote small integers:
+ o(0x13001c00 | (bt == VT_SHORT) << 13 |
+ !!(rt & VT_UNSIGNED) << 30); // [su]xt[bh] w0,w0
+ else if (bt == VT_STRUCT && !(a[0] & 1)) {
+ // A struct was returned in registers, so write it out:
+ gv(RC_R(8));
+ --vtop;
+ if (a[0] == 0) {
+ int align, size = type_size(return_type, &align);
+ assert(size <= 16);
+ if (size > 8)
+ o(0xa9000500); // stp x0,x1,[x8]
+ else if (size)
+ arm64_strx(size > 4 ? 3 : size > 2 ? 2 : size > 1, 0, 8, 0);
+
+ }
+ else if (a[0] == 16) {
+ int j, sz, n = arm64_hfa(return_type, &sz);
+ for (j = 0; j < n; j++)
+ o(0x3d000100 |
+ (sz & 16) << 19 | -(sz & 8) << 27 | (sz & 4) << 29 |
+ (a[i] / 2 - 8 + j) |
+ j << 10); // str ([sdq])(*),[x8,#(j * sz)]
+ }
+ }
+ }
+
+ tcc_free(a1);
+ tcc_free(a);
+ tcc_free(t);
+}
+
+static unsigned long arm64_func_va_list_stack;
+static int arm64_func_va_list_gr_offs;
+static int arm64_func_va_list_vr_offs;
+static int arm64_func_sub_sp_offset;
+
+ST_FUNC void gfunc_prolog(CType *func_type)
+{
+ int n = 0;
+ int i = 0;
+ Sym *sym;
+ CType **t;
+ unsigned long *a;
+
+ // Why doesn't the caller (gen_function) set func_vt?
+ func_vt = func_type->ref->type;
+ func_vc = 144; // offset of where x8 is stored
+
+ for (sym = func_type->ref; sym; sym = sym->next)
+ ++n;
+ t = tcc_malloc(n * sizeof(*t));
+ a = tcc_malloc(n * sizeof(*a));
+
+ for (sym = func_type->ref; sym; sym = sym->next)
+ t[i++] = &sym->type;
+
+ arm64_func_va_list_stack = arm64_pcs(n - 1, t, a);
+
+ o(0xa9b27bfd); // stp x29,x30,[sp,#-224]!
+ o(0xad0087e0); // stp q0,q1,[sp,#16]
+ o(0xad018fe2); // stp q2,q3,[sp,#48]
+ o(0xad0297e4); // stp q4,q5,[sp,#80]
+ o(0xad039fe6); // stp q6,q7,[sp,#112]
+ o(0xa90923e8); // stp x8,x8,[sp,#144]
+ o(0xa90a07e0); // stp x0,x1,[sp,#160]
+ o(0xa90b0fe2); // stp x2,x3,[sp,#176]
+ o(0xa90c17e4); // stp x4,x5,[sp,#192]
+ o(0xa90d1fe6); // stp x6,x7,[sp,#208]
+
+ arm64_func_va_list_gr_offs = -64;
+ arm64_func_va_list_vr_offs = -128;
+
+ for (i = 1, sym = func_type->ref->next; sym; i++, sym = sym->next) {
+ int off = (a[i] < 16 ? 160 + a[i] / 2 * 8 :
+ a[i] < 32 ? 16 + (a[i] - 16) / 2 * 16 :
+ 224 + ((a[i] - 32) >> 1 << 1));
+ sym_push(sym->v & ~SYM_FIELD, &sym->type,
+ (a[i] & 1 ? VT_LLOCAL : VT_LOCAL) | lvalue_type(sym->type.t),
+ off);
+
+ if (a[i] < 16) {
+ int align, size = type_size(&sym->type, &align);
+ arm64_func_va_list_gr_offs = (a[i] / 2 - 7 +
+ (!(a[i] & 1) && size > 8)) * 8;
+ }
+ else if (a[i] < 32) {
+ int hfa = arm64_hfa(&sym->type, 0);
+ arm64_func_va_list_vr_offs = (a[i] / 2 - 16 +
+ (hfa ? hfa : 1)) * 16;
+ }
+
+ // HFAs of float and double need to be written differently:
+ if (16 <= a[i] && a[i] < 32 && (sym->type.t & VT_BTYPE) == VT_STRUCT) {
+ int j, sz, k = arm64_hfa(&sym->type, &sz);
+ if (sz < 16)
+ for (j = 0; j < k; j++) {
+ o(0x3d0003e0 | -(sz & 8) << 27 | (sz & 4) << 29 |
+ ((a[i] - 16) / 2 + j) | (off / sz + j) << 10);
+ // str ([sdq])(*),[sp,#(j * sz)]
+ }
+ }
+ }
+
+ tcc_free(a);
+ tcc_free(t);
+
+ o(0x910003fd); // mov x29,sp
+ arm64_func_sub_sp_offset = ind;
+ // In gfunc_epilog these will be replaced with code to decrement SP:
+ o(0xd503201f); // nop
+ o(0xd503201f); // nop
+ loc = 0;
+}
+
+ST_FUNC void gen_va_start(void)
+{
+ int r;
+ --vtop; // we don't need the "arg"
+ gaddrof();
+ r = intr(gv(RC_INT));
+
+ if (arm64_func_va_list_stack) {
+ //xx could use add (immediate) here
+ arm64_movimm(30, arm64_func_va_list_stack + 224);
+ o(0x8b1e03be); // add x30,x29,x30
+ }
+ else
+ o(0x910383be); // add x30,x29,#224
+ o(0xf900001e | r << 5); // str x30,[x(r)]
+
+ if (arm64_func_va_list_gr_offs) {
+ if (arm64_func_va_list_stack)
+ o(0x910383be); // add x30,x29,#224
+ o(0xf900041e | r << 5); // str x30,[x(r),#8]
+ }
+
+ if (arm64_func_va_list_vr_offs) {
+ o(0x910243be); // add x30,x29,#144
+ o(0xf900081e | r << 5); // str x30,[x(r),#16]
+ }
+
+ arm64_movimm(30, arm64_func_va_list_gr_offs);
+ o(0xb900181e | r << 5); // str w30,[x(r),#24]
+
+ arm64_movimm(30, arm64_func_va_list_vr_offs);
+ o(0xb9001c1e | r << 5); // str w30,[x(r),#28]
+
+ --vtop;
+}
+
+ST_FUNC void gen_va_arg(CType *t)
+{
+ int align, size = type_size(t, &align);
+ int fsize, hfa = arm64_hfa(t, &fsize);
+ uint32_t r0, r1;
+
+ if (is_float(t->t)) {
+ hfa = 1;
+ fsize = size;
+ }
+
+ gaddrof();
+ r0 = intr(gv(RC_INT));
+ r1 = get_reg(RC_INT);
+ vtop[0].r = r1 | lvalue_type(t->t);
+ r1 = intr(r1);
+
+ if (!hfa) {
+ uint32_t n = size > 16 ? 8 : (size + 7) & -8;
+ o(0xb940181e | r0 << 5); // ldr w30,[x(r0),#24] // __gr_offs
+ if (align == 16) {
+ assert(0); // this path untested but needed for __uint128_t
+ o(0x11003fde); // add w30,w30,#15
+ o(0x121c6fde); // and w30,w30,#-16
+ }
+ o(0x310003c0 | r1 | n << 10); // adds w(r1),w30,#(n)
+ o(0x540000ad); // b.le .+20
+ o(0xf9400000 | r1 | r0 << 5); // ldr x(r1),[x(r0)] // __stack
+ o(0x9100001e | r1 << 5 | n << 10); // add x30,x(r1),#(n)
+ o(0xf900001e | r0 << 5); // str x30,[x(r0)] // __stack
+ o(0x14000004); // b .+16
+ o(0xb9001800 | r1 | r0 << 5); // str w(r1),[x(r0),#24] // __gr_offs
+ o(0xf9400400 | r1 | r0 << 5); // ldr x(r1),[x(r0),#8] // __gr_top
+ o(0x8b3ec000 | r1 | r1 << 5); // add x(r1),x(r1),w30,sxtw
+ if (size > 16)
+ o(0xf9400000 | r1 | r1 << 5); // ldr x(r1),[x(r1)]
+ }
+ else {
+ uint32_t rsz = hfa << 4;
+ uint32_t ssz = (size + 7) & -(uint32_t)8;
+ uint32_t b1, b2;
+ o(0xb9401c1e | r0 << 5); // ldr w30,[x(r0),#28] // __vr_offs
+ o(0x310003c0 | r1 | rsz << 10); // adds w(r1),w30,#(rsz)
+ b1 = ind; o(0x5400000d); // b.le lab1
+ o(0xf9400000 | r1 | r0 << 5); // ldr x(r1),[x(r0)] // __stack
+ if (fsize == 16) {
+ o(0x91003c00 | r1 | r1 << 5); // add x(r1),x(r1),#15
+ o(0x927cec00 | r1 | r1 << 5); // and x(r1),x(r1),#-16
+ }
+ o(0x9100001e | r1 << 5 | ssz << 10); // add x30,x(r1),#(ssz)
+ o(0xf900001e | r0 << 5); // str x30,[x(r0)] // __stack
+ b2 = ind; o(0x14000000); // b lab2
+ // lab1:
+ *(uint32_t *)(cur_text_section->data + b1) =
+ (0x5400000d | (ind - b1) << 3);
+ o(0xb9001c00 | r1 | r0 << 5); // str w(r1),[x(r0),#28] // __vr_offs
+ o(0xf9400800 | r1 | r0 << 5); // ldr x(r1),[x(r0),#16] // __vr_top
+ if (hfa == 1 || fsize == 16)
+ o(0x8b3ec000 | r1 | r1 << 5); // add x(r1),x(r1),w30,sxtw
+ else {
+ // We need to change the layout of this HFA.
+ // Get some space on the stack using global variable "loc":
+ loc = (loc - size) & -(uint32_t)align;
+ o(0x8b3ec000 | 30 | r1 << 5); // add x30,x(r1),w30,sxtw
+ arm64_movimm(r1, loc);
+ o(0x8b0003a0 | r1 | r1 << 16); // add x(r1),x29,x(r1)
+ o(0x4c402bdc | (uint32_t)fsize << 7 |
+ (uint32_t)(hfa == 2) << 15 |
+ (uint32_t)(hfa == 3) << 14); // ld1 {v28.(4s|2d),...},[x30]
+ o(0x0d00801c | r1 << 5 | (fsize == 8) << 10 |
+ (uint32_t)(hfa != 2) << 13 |
+ (uint32_t)(hfa != 3) << 21); // st(hfa) {v28.(s|d),...}[0],[x(r1)]
+ }
+ // lab2:
+ *(uint32_t *)(cur_text_section->data + b2) =
+ (0x14000000 | (ind - b2) >> 2);
+ }
+}
+
+ST_FUNC int regargs_nregs(RegArgs *args)
+{
+ return *args;
+}
+
+ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *align, int *regsize, RegArgs *args)
+{
+ *args = 0;
+
+ return 0;
+}
+
+ST_FUNC void greturn(void)
+{
+ CType *t = &func_vt;
+ unsigned long a;
+
+ arm64_pcs(0, &t, &a);
+ switch (a) {
+ case -1:
+ break;
+ case 0:
+ if ((func_vt.t & VT_BTYPE) == VT_STRUCT) {
+ int align, size = type_size(&func_vt, &align);
+ gaddrof();
+ gv(RC_R(0));
+ arm64_ldrs(0, size);
+ }
+ else
+ gv(RC_IRET);
+ break;
+ case 1: {
+ CType type = func_vt;
+ mk_pointer(&type);
+ vset(&type, VT_LOCAL | VT_LVAL, func_vc);
+ indir();
+ vswap();
+ vstore();
+ break;
+ }
+ case 16:
+ if ((func_vt.t & VT_BTYPE) == VT_STRUCT) {
+ int j, sz, n = arm64_hfa(&vtop->type, &sz);
+ gaddrof();
+ gv(RC_R(0));
+ for (j = 0; j < n; j++)
+ o(0x3d400000 |
+ (sz & 16) << 19 | -(sz & 8) << 27 | (sz & 4) << 29 |
+ j | j << 10); // ldr ([sdq])(*),[x0,#(j * sz)]
+ }
+ else
+ gv(RC_FRET);
+ break;
+ default:
+ assert(0);
+ }
+}
+
+ST_FUNC void gfunc_epilog(void)
+{
+ if (loc) {
+ // Insert instructions to subtract size of stack frame from SP.
+ uint32_t *ptr =
+ (uint32_t *)(cur_text_section->data + arm64_func_sub_sp_offset);
+ uint64_t diff = (-loc + 15) & ~15;
+ if (!(diff >> 24)) {
+ if (diff & 0xfff) // sub sp,sp,#(diff & 0xfff)
+ ptr[0] = 0xd10003ff | (diff & 0xfff) << 10;
+ if (diff >> 12) // sub sp,sp,#(diff >> 12),lsl #12
+ ptr[1] = 0xd14003ff | (diff >> 12) << 10;
+ }
+ else {
+ // In this case we may subtract more than necessary,
+ // but always less than 17/16 of what we were aiming for.
+ int i = 0;
+ int j = 0;
+ while (diff >> 20) {
+ diff = (diff + 0xffff) >> 16;
+ ++i;
+ }
+ while (diff >> 16) {
+ diff = (diff + 1) >> 1;
+ ++j;
+ }
+ ptr[0] = 0xd2800010 | diff << 5 | i << 21;
+ // mov x16,#(diff),lsl #(16 * i)
+ ptr[1] = 0xcb3063ff | j << 10;
+ // sub sp,sp,x16,lsl #(j)
+ }
+ }
+ o(0x910003bf); // mov sp,x29
+ o(0xa8ce7bfd); // ldp x29,x30,[sp],#224
+
+ o(0xd65f03c0); // ret
+}
+
+// Generate forward branch to label:
+ST_FUNC int gjmp(int t)
+{
+ int r = ind;
+ o(t);
+ return r;
+}
+
+// Generate branch to known address:
+ST_FUNC void gjmp_addr(int a)
+{
+ assert(a - ind + 0x8000000 < 0x10000000);
+ o(0x14000000 | ((a - ind) >> 2 & 0x3ffffff));
+}
+
+ST_FUNC int gtst(int inv, int t)
+{
+ int bt = vtop->type.t & VT_BTYPE;
+ if (bt == VT_LDOUBLE) {
+ int a, b, f = fltr(gv(RC_FLOAT));
+ a = get_reg(RC_INT);
+ vpushi(0);
+ vtop[0].r = a;
+ b = get_reg(RC_INT);
+ a = intr(a);
+ b = intr(b);
+ o(0x4e083c00 | a | f << 5); // mov x(a),v(f).d[0]
+ o(0x4e183c00 | b | f << 5); // mov x(b),v(f).d[1]
+ o(0xaa000400 | a | a << 5 | b << 16); // orr x(a),x(a),x(b),lsl #1
+ o(0xb4000040 | a | !!inv << 24); // cbz/cbnz x(a),.+8
+ --vtop;
+ }
+ else if (bt == VT_FLOAT || bt == VT_DOUBLE) {
+ int a = fltr(gv(RC_FLOAT));
+ o(0x1e202008 | a << 5 | (bt != VT_FLOAT) << 22); // fcmp
+ o(0x54000040 | !!inv); // b.eq/b.ne .+8
+ }
+ else {
+ int ll = (bt == VT_PTR || bt == VT_LLONG);
+ int a = intr(gv(RC_INT));
+ o(0x34000040 | a | !!inv << 24 | ll << 31); // cbz/cbnz wA,.+8
+ }
+ --vtop;
+ return gjmp(t);
+}
+
+static int arm64_iconst(uint64_t *val, SValue *sv)
+{
+ if ((sv->r & (VT_VALMASK | VT_LVAL | VT_SYM)) != VT_CONST)
+ return 0;
+ if (val) {
+ int t = sv->type.t & (VT_BTYPE | VT_UNSIGNED);
+ // It's crazy how TCC has all these alternatives for storing a value:
+ if (t == (VT_LLONG | VT_UNSIGNED))
+ *val = sv->c.ull;
+ else if (t == VT_LLONG)
+ *val = sv->c.ll;
+ else if (t & VT_UNSIGNED)
+ *val = sv->c.ui;
+ else
+ *val = sv->c.i;
+ }
+ return 1;
+}
+
+static int arm64_gen_opic(int op, uint32_t l, int rev, uint64_t val,
+ uint32_t x, uint32_t a)
+{
+ if (op == '-' && !rev) {
+ val = -val;
+ op = '+';
+ }
+ val = l ? val : (uint32_t)val;
+
+ switch (op) {
+
+ case '+': {
+ int s = l ? val >> 63 : val >> 31;
+ val = s ? -val : val;
+ val = l ? val : (uint32_t)val;
+ if (!(val & ~(uint64_t)0xfff))
+ o(0x11000000 | l << 31 | s << 30 | x | a << 5 | val << 10);
+ else if (!(val & ~(uint64_t)0xfff000))
+ o(0x11400000 | l << 31 | s << 30 | x | a << 5 | val >> 12 << 10);
+ else {
+ arm64_movimm(30, val); // use x30
+ o(0x0b1e0000 | l << 31 | s << 30 | x | a << 5);
+ }
+ return 1;
+ }
+
+ case '-':
+ if (!val)
+ o(0x4b0003e0 | l << 31 | x | a << 16); // neg
+ else if (val == (l ? (uint64_t)-1 : (uint32_t)-1))
+ o(0x2a2003e0 | l << 31 | x | a << 16); // mvn
+ else {
+ arm64_movimm(30, val); // use x30
+ o(0x4b0003c0 | l << 31 | x | a << 16); // sub
+ }
+ return 1;
+
+ case '^':
+ if (val == -1 || (val == 0xffffffff && !l)) {
+ o(0x2a2003e0 | l << 31 | x | a << 16); // mvn
+ return 1;
+ }
+ // fall through
+ case '&':
+ case '|': {
+ int e = arm64_encode_bimm64(l ? val : val | val << 32);
+ if (e < 0)
+ return 0;
+ o((op == '&' ? 0x12000000 :
+ op == '|' ? 0x32000000 : 0x52000000) |
+ l << 31 | x | a << 5 | (uint32_t)e << 10);
+ return 1;
+ }
+
+ case TOK_SAR:
+ case TOK_SHL:
+ case TOK_SHR: {
+ uint32_t n = 32 << l;
+ val = val & (n - 1);
+ if (rev)
+ return 0;
+ if (!val)
+ assert(0);
+ else if (op == TOK_SHL)
+ o(0x53000000 | l << 31 | l << 22 | x | a << 5 |
+ (n - val) << 16 | (n - 1 - val) << 10); // lsl
+ else
+ o(0x13000000 | (op == TOK_SHR) << 30 | l << 31 | l << 22 |
+ x | a << 5 | val << 16 | (n - 1) << 10); // lsr/asr
+ return 1;
+ }
+
+ }
+ return 0;
+}
+
+static void arm64_gen_opil(int op, uint32_t l)
+{
+ uint32_t x, a, b;
+
+ // Special treatment for operations with a constant operand:
+ {
+ uint64_t val;
+ int rev = 1;
+
+ if (arm64_iconst(0, &vtop[0])) {
+ vswap();
+ rev = 0;
+ }
+ if (arm64_iconst(&val, &vtop[-1])) {
+ gv(RC_INT);
+ a = intr(vtop[0].r);
+ --vtop;
+ x = get_reg(RC_INT);
+ ++vtop;
+ if (arm64_gen_opic(op, l, rev, val, intr(x), a)) {
+ vtop[0].r = x;
+ vswap();
+ --vtop;
+ return;
+ }
+ }
+ if (!rev)
+ vswap();
+ }
+
+ gv2(RC_INT, RC_INT);
+ assert(vtop[-1].r < VT_CONST && vtop[0].r < VT_CONST);
+ a = intr(vtop[-1].r);
+ b = intr(vtop[0].r);
+ vtop -= 2;
+ x = get_reg(RC_INT);
+ ++vtop;
+ vtop[0].r = x;
+ x = intr(x);
+
+ switch (op) {
+ case '%':
+ // Use x30 for quotient:
+ o(0x1ac00c00 | l << 31 | 30 | a << 5 | b << 16); // sdiv
+ o(0x1b008000 | l << 31 | x | 30 << 5 | b << 16 | a << 10); // msub
+ break;
+ case '&':
+ o(0x0a000000 | l << 31 | x | a << 5 | b << 16); // and
+ break;
+ case '*':
+ o(0x1b007c00 | l << 31 | x | a << 5 | b << 16); // mul
+ break;
+ case '+':
+ o(0x0b000000 | l << 31 | x | a << 5 | b << 16); // add
+ break;
+ case '-':
+ o(0x4b000000 | l << 31 | x | a << 5 | b << 16); // sub
+ break;
+ case '/':
+ o(0x1ac00c00 | l << 31 | x | a << 5 | b << 16); // sdiv
+ break;
+ case '^':
+ o(0x4a000000 | l << 31 | x | a << 5 | b << 16); // eor
+ break;
+ case '|':
+ o(0x2a000000 | l << 31 | x | a << 5 | b << 16); // orr
+ break;
+ case TOK_EQ:
+ o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
+ o(0x1a9f17e0 | x); // cset wA,eq
+ break;
+ case TOK_GE:
+ o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
+ o(0x1a9fb7e0 | x); // cset wA,ge
+ break;
+ case TOK_GT:
+ o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
+ o(0x1a9fd7e0 | x); // cset wA,gt
+ break;
+ case TOK_LE:
+ o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
+ o(0x1a9fc7e0 | x); // cset wA,le
+ break;
+ case TOK_LT:
+ o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
+ o(0x1a9fa7e0 | x); // cset wA,lt
+ break;
+ case TOK_NE:
+ o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
+ o(0x1a9f07e0 | x); // cset wA,ne
+ break;
+ case TOK_SAR:
+ o(0x1ac02800 | l << 31 | x | a << 5 | b << 16); // asr
+ break;
+ case TOK_SHL:
+ o(0x1ac02000 | l << 31 | x | a << 5 | b << 16); // lsl
+ break;
+ case TOK_SHR:
+ o(0x1ac02400 | l << 31 | x | a << 5 | b << 16); // lsr
+ break;
+ case TOK_UDIV:
+ case TOK_PDIV:
+ o(0x1ac00800 | l << 31 | x | a << 5 | b << 16); // udiv
+ break;
+ case TOK_UGE:
+ o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
+ o(0x1a9f37e0 | x); // cset wA,cs
+ break;
+ case TOK_UGT:
+ o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
+ o(0x1a9f97e0 | x); // cset wA,hi
+ break;
+ case TOK_ULT:
+ o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
+ o(0x1a9f27e0 | x); // cset wA,cc
+ break;
+ case TOK_ULE:
+ o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
+ o(0x1a9f87e0 | x); // cset wA,ls
+ break;
+ case TOK_UMOD:
+ // Use x30 for quotient:
+ o(0x1ac00800 | l << 31 | 30 | a << 5 | b << 16); // udiv
+ o(0x1b008000 | l << 31 | x | 30 << 5 | b << 16 | a << 10); // msub
+ break;
+ default:
+ assert(0);
+ }
+}
+
+ST_FUNC void gen_opi(int op)
+{
+ arm64_gen_opil(op, 0);
+}
+
+ST_FUNC void gen_opl(int op)
+{
+ arm64_gen_opil(op, 1);
+}
+
+ST_FUNC void gen_opf(int op)
+{
+ int x, a, b, dbl;
+
+ if (vtop[0].type.t == VT_LDOUBLE) {
+ CType type = vtop[0].type;
+ int func = 0;
+ int cond = -1;
+ switch (op) {
+ case '*': func = TOK___multf3; break;
+ case '+': func = TOK___addtf3; break;
+ case '-': func = TOK___subtf3; break;
+ case '/': func = TOK___divtf3; break;
+ case TOK_EQ: func = TOK___eqtf2; cond = 1; break;
+ case TOK_NE: func = TOK___netf2; cond = 0; break;
+ case TOK_LT: func = TOK___lttf2; cond = 10; break;
+ case TOK_GE: func = TOK___getf2; cond = 11; break;
+ case TOK_LE: func = TOK___letf2; cond = 12; break;
+ case TOK_GT: func = TOK___gttf2; cond = 13; break;
+ default: assert(0); break;
+ }
+ vpush_global_sym(&func_old_type, func);
+ vrott(3);
+ gfunc_call(2);
+ vpushi(0);
+ vtop->r = cond < 0 ? REG_FRET : REG_IRET;
+ if (cond < 0)
+ vtop->type = type;
+ else {
+ o(0x7100001f); // cmp w0,#0
+ o(0x1a9f07e0 | cond << 12); // cset w0,(cond)
+ }
+ return;
+ }
+
+ dbl = vtop[0].type.t != VT_FLOAT;
+ gv2(RC_FLOAT, RC_FLOAT);
+ assert(vtop[-1].r < VT_CONST && vtop[0].r < VT_CONST);
+ a = fltr(vtop[-1].r);
+ b = fltr(vtop[0].r);
+ vtop -= 2;
+ switch (op) {
+ case TOK_EQ: case TOK_NE:
+ case TOK_LT: case TOK_GE: case TOK_LE: case TOK_GT:
+ x = get_reg(RC_INT);
+ ++vtop;
+ vtop[0].r = x;
+ x = intr(x);
+ break;
+ default:
+ x = get_reg(RC_FLOAT);
+ ++vtop;
+ vtop[0].r = x;
+ x = fltr(x);
+ break;
+ }
+
+ switch (op) {
+ case '*':
+ o(0x1e200800 | dbl << 22 | x | a << 5 | b << 16); // fmul
+ break;
+ case '+':
+ o(0x1e202800 | dbl << 22 | x | a << 5 | b << 16); // fadd
+ break;
+ case '-':
+ o(0x1e203800 | dbl << 22 | x | a << 5 | b << 16); // fsub
+ break;
+ case '/':
+ o(0x1e201800 | dbl << 22 | x | a << 5 | b << 16); // fdiv
+ break;
+ case TOK_EQ:
+ o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
+ o(0x1a9f17e0 | x); // cset w(x),eq
+ break;
+ case TOK_GE:
+ o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
+ o(0x1a9fb7e0 | x); // cset w(x),ge
+ break;
+ case TOK_GT:
+ o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
+ o(0x1a9fd7e0 | x); // cset w(x),gt
+ break;
+ case TOK_LE:
+ o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
+ o(0x1a9f87e0 | x); // cset w(x),ls
+ break;
+ case TOK_LT:
+ o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
+ o(0x1a9f57e0 | x); // cset w(x),mi
+ break;
+ case TOK_NE:
+ o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
+ o(0x1a9f07e0 | x); // cset w(x),ne
+ break;
+ default:
+ assert(0);
+ }
+}
+
+// Generate sign extension from 32 to 64 bits:
+ST_FUNC void gen_cvt_sxtw(void)
+{
+ int r = intr(gv(RC_INT));
+ o(0x93407c00 | r | r << 5); // sxtw x(r),w(r)
+}
+
+ST_FUNC void gen_cvt_itof(int t)
+{
+ if (t == VT_LDOUBLE) {
+ int f = vtop->type.t;
+ int func = (f & VT_BTYPE) == VT_LLONG ?
+ (f & VT_UNSIGNED ? TOK___floatunditf : TOK___floatditf) :
+ (f & VT_UNSIGNED ? TOK___floatunsitf : TOK___floatsitf);
+ vpush_global_sym(&func_old_type, func);
+ vrott(2);
+ gfunc_call(1);
+ vpushi(0);
+ vtop->type.t = t;
+ vtop->r = REG_FRET;
+ return;
+ }
+ else {
+ int d, n = intr(gv(RC_INT));
+ int s = !(vtop->type.t & VT_UNSIGNED);
+ int l = ((vtop->type.t & VT_BTYPE) == VT_LLONG);
+ --vtop;
+ d = get_reg(RC_FLOAT);
+ ++vtop;
+ vtop[0].r = d;
+ o(0x1e220000 | !s << 16 | (t != VT_FLOAT) << 22 | fltr(d) |
+ l << 31 | n << 5); // [us]cvtf [sd](d),[wx](n)
+ }
+}
+
+ST_FUNC void gen_cvt_ftoi(int t)
+{
+ if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
+ int func = (t & VT_BTYPE) == VT_LLONG ?
+ (t & VT_UNSIGNED ? TOK___fixunstfdi : TOK___fixtfdi) :
+ (t & VT_UNSIGNED ? TOK___fixunstfsi : TOK___fixtfsi);
+ vpush_global_sym(&func_old_type, func);
+ vrott(2);
+ gfunc_call(1);
+ vpushi(0);
+ vtop->type.t = t;
+ vtop->r = REG_IRET;
+ return;
+ }
+ else {
+ int d, n = fltr(gv(RC_FLOAT));
+ int l = ((vtop->type.t & VT_BTYPE) != VT_FLOAT);
+ --vtop;
+ d = get_reg(RC_INT);
+ ++vtop;
+ vtop[0].r = d;
+ o(0x1e380000 |
+ !!(t & VT_UNSIGNED) << 16 |
+ ((t & VT_BTYPE) == VT_LLONG) << 31 | intr(d) |
+ l << 22 | n << 5); // fcvtz[su] [wx](d),[sd](n)
+ }
+}
+
+ST_FUNC void gen_cvt_ftof(int t)
+{
+ int f = vtop[0].type.t;
+ assert(t == VT_FLOAT || t == VT_DOUBLE || t == VT_LDOUBLE);
+ assert(f == VT_FLOAT || f == VT_DOUBLE || f == VT_LDOUBLE);
+ if (t == f)
+ return;
+
+ if (t == VT_LDOUBLE || f == VT_LDOUBLE) {
+ int func = (t == VT_LDOUBLE) ?
+ (f == VT_FLOAT ? TOK___extendsftf2 : TOK___extenddftf2) :
+ (t == VT_FLOAT ? TOK___trunctfsf2 : TOK___trunctfdf2);
+ vpush_global_sym(&func_old_type, func);
+ vrott(2);
+ gfunc_call(1);
+ vpushi(0);
+ vtop->type.t = t;
+ vtop->r = REG_FRET;
+ }
+ else {
+ int x, a;
+ gv(RC_FLOAT);
+ assert(vtop[0].r < VT_CONST);
+ a = fltr(vtop[0].r);
+ --vtop;
+ x = get_reg(RC_FLOAT);
+ ++vtop;
+ vtop[0].r = x;
+ x = fltr(x);
+
+ if (f == VT_FLOAT)
+ o(0x1e22c000 | x | a << 5); // fcvt d(x),s(a)
+ else
+ o(0x1e624000 | x | a << 5); // fcvt s(x),d(a)
+ }
+}
+
+ST_FUNC void ggoto(void)
+{
+ arm64_gen_bl_or_b(1);
+ --vtop;
+}
+
+ST_FUNC void gen_clear_cache(void)
+{
+ uint32_t beg, end, dsz, isz, p, lab1, b1;
+ gv2(RC_INT, RC_INT);
+ vpushi(0);
+ vtop->r = get_reg(RC_INT);
+ vpushi(0);
+ vtop->r = get_reg(RC_INT);
+ vpushi(0);
+ vtop->r = get_reg(RC_INT);
+ beg = intr(vtop[-4].r); // x0
+ end = intr(vtop[-3].r); // x1
+ dsz = intr(vtop[-2].r); // x2
+ isz = intr(vtop[-1].r); // x3
+ p = intr(vtop[0].r); // x4
+ vtop -= 5;
+
+ o(0xd53b0020 | isz); // mrs x(isz),ctr_el0
+ o(0x52800080 | p); // mov w(p),#4
+ o(0x53104c00 | dsz | isz << 5); // ubfx w(dsz),w(isz),#16,#4
+ o(0x1ac02000 | dsz | p << 5 | dsz << 16); // lsl w(dsz),w(p),w(dsz)
+ o(0x12000c00 | isz | isz << 5); // and w(isz),w(isz),#15
+ o(0x1ac02000 | isz | p << 5 | isz << 16); // lsl w(isz),w(p),w(isz)
+ o(0x51000400 | p | dsz << 5); // sub w(p),w(dsz),#1
+ o(0x8a240004 | p | beg << 5 | p << 16); // bic x(p),x(beg),x(p)
+ b1 = ind; o(0x14000000); // b
+ lab1 = ind;
+ o(0xd50b7b20 | p); // dc cvau,x(p)
+ o(0x8b000000 | p | p << 5 | dsz << 16); // add x(p),x(p),x(dsz)
+ *(uint32_t *)(cur_text_section->data + b1) =
+ (0x14000000 | (ind - b1) >> 2);
+ o(0xeb00001f | p << 5 | end << 16); // cmp x(p),x(end)
+ o(0x54ffffa3 | ((lab1 - ind) << 3 & 0xffffe0)); // b.cc lab1
+ o(0xd5033b9f); // dsb ish
+ o(0x51000400 | p | isz << 5); // sub w(p),w(isz),#1
+ o(0x8a240004 | p | beg << 5 | p << 16); // bic x(p),x(beg),x(p)
+ b1 = ind; o(0x14000000); // b
+ lab1 = ind;
+ o(0xd50b7520 | p); // ic ivau,x(p)
+ o(0x8b000000 | p | p << 5 | isz << 16); // add x(p),x(p),x(isz)
+ *(uint32_t *)(cur_text_section->data + b1) =
+ (0x14000000 | (ind - b1) >> 2);
+ o(0xeb00001f | p << 5 | end << 16); // cmp x(p),x(end)
+ o(0x54ffffa3 | ((lab1 - ind) << 3 & 0xffffe0)); // b.cc lab1
+ o(0xd5033b9f); // dsb ish
+ o(0xd5033fdf); // isb
+}
+
+ST_FUNC void gen_vla_sp_save(int addr) {
+ tcc_error("variable length arrays unsupported for this target");
+}
+
+ST_FUNC void gen_vla_sp_restore(int addr) {
+ tcc_error("variable length arrays unsupported for this target");
+}
+
+ST_FUNC void gen_vla_alloc(CType *type, int align) {
+ tcc_error("variable length arrays unsupported for this target");
+}
+
+/* end of A64 code generator */
+/*************************************************************/
+#endif
+/*************************************************************/