diff options
| -rw-r--r-- | tests/asmtest.S | 2 | ||||
| -rw-r--r-- | x86_64-asm.h | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/tests/asmtest.S b/tests/asmtest.S index 7f2e4ca..aed99ed 100644 --- a/tests/asmtest.S +++ b/tests/asmtest.S @@ -614,6 +614,8 @@ int $0x10 mfence sfence clflush 0x1000(%rax,%rcx) + fxsaveq (%rdx) + fxrstorq (%rcx) #endif emms diff --git a/x86_64-asm.h b/x86_64-asm.h index c590c57..ef04d02 100644 --- a/x86_64-asm.h +++ b/x86_64-asm.h @@ -347,6 +347,12 @@ ALT(DEF_ASM_OP1(fstsw, 0xdd, 7, OPC_MODRM | OPC_FWAIT, OPT_EA )) DEF_ASM_OP1(ffreep, 0xdfc0, 4, OPC_REG, OPT_ST ) DEF_ASM_OP1(fxsave, 0x0fae, 0, OPC_MODRM, OPT_EA ) DEF_ASM_OP1(fxrstor, 0x0fae, 1, OPC_MODRM, OPT_EA ) + /* The *q forms of fxrstor/fxsave use a REX prefix. + If the operand would use extended registers we would have to modify + it instead of generating a second one. Currently that's no + problem with TCC, we don't use extended registers. */ + DEF_ASM_OP1(fxsaveq, 0x480fae, 0, OPC_MODRM, OPT_EA ) + DEF_ASM_OP1(fxrstorq, 0x480fae, 1, OPC_MODRM, OPT_EA ) /* segments */ DEF_ASM_OP2(arpl, 0x63, 0, OPC_MODRM, OPT_REG16, OPT_REG16 | OPT_EA) |