Architecture-specific section alignment

Tests found excessive cache thrashing on x86-64 architectures. The
problem was traced to the alignment of sections. This patch sets up
an architecture-specific alignment of 512 bytes for x86-64 and 16
bytes for all others. It uses preprocessor directives that, hopefully,
make it easy to tweak for other architectures.

1 files changed, 7 insertions, 1 deletions

diff --git a/tccrun.c b/tccrun.c
index 7eb47fc..517205e 100644
--- a/tccrun.c
+++ b/tccrun.c
@@ -174,6 +174,12 @@ LIBTCCAPI int tcc_run(TCCState *s1, int argc, char **argv)
     return (*prog_main)(argc, argv);
 }
 
+#ifdef TCC_TARGET_X86_64
+ #define SECTION_ALIGNMENT 511
+#else
+ #define SECTION_ALIGNMENT 15
+#endif
+
 /* relocate code. Return -1 on error, required size if ptr is NULL,
    otherwise copy code into buffer passed by the caller */
 static int tcc_relocate_ex(TCCState *s1, void *ptr)
@@ -205,7 +211,7 @@ static int tcc_relocate_ex(TCCState *s1, void *ptr)
         s = s1->sections[i];
         if (0 == (s->sh_flags & SHF_ALLOC))
             continue;
-        offset = (offset + 15) & ~15;
+        offset = (offset + SECTION_ALIGNMENT) & ~SECTION_ALIGNMENT;
         s->sh_addr = mem ? mem + offset : 0;
         offset += s->data_offset;
     }