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| author | grischka <grischka> | 2017-07-09 12:34:11 +0200 |
|---|---|---|
| committer | grischka <grischka> | 2017-07-09 12:34:11 +0200 |
| commit | 9ba76ac834608f76b734674048a7cc4334051e32 (patch) | |
| tree | 8d71dd52664d0399fb010fd502283993b0d67285 /arm64-gen.c | |
| parent | 9f79b62ec4d84d07cf4a2fba969cb67c8f6ed8e5 (diff) | |
| download | tinycc-9ba76ac834608f76b734674048a7cc4334051e32.tar.gz tinycc-9ba76ac834608f76b734674048a7cc4334051e32.tar.bz2 | |
refactor sym & attributes
tcc.h:
* cleanup struct 'Sym'
* include some 'Attributes' into 'Sym'
* in turn get rid of VT_IM/EXPORT, VT_WEAK
* re-number VT_XXX flags
* replace some 'long' function args by 'int'
tccgen.c:
* refactor parse_btype()
Diffstat (limited to 'arm64-gen.c')
| -rw-r--r-- | arm64-gen.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arm64-gen.c b/arm64-gen.c index c7a71e6..1ebbd2b 100644 --- a/arm64-gen.c +++ b/arm64-gen.c @@ -428,7 +428,7 @@ static void arm64_sym(int r, Sym *sym, unsigned long addend) // relocation and use only relocations with unlimited range. int avoid_adrp = 1; - if (avoid_adrp || (sym->type.t & VT_WEAK)) { + if (avoid_adrp || sym->a.weak) { // (GCC uses a R_AARCH64_ABS64 in this case.) greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G0_NC, addend); o(0xd2800000 | r); // mov x(rt),#0,lsl #0 |