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| author | Michael Matz <matz@suse.de> | 2016-05-12 00:57:02 +0200 |
|---|---|---|
| committer | Michael Matz <matz@suse.de> | 2016-05-12 00:57:02 +0200 |
| commit | 6bd8c936e33db20f7023e11228bc2f2a4fb51f2e (patch) | |
| tree | 46b0f7e21a1c78f17feb8e0b541018f358f962c0 | |
| parent | b9f01dffc61d41868157d3cc31f460d952502779 (diff) | |
| download | tinycc-6bd8c936e33db20f7023e11228bc2f2a4fb51f2e.tar.gz tinycc-6bd8c936e33db20f7023e11228bc2f2a4fb51f2e.tar.bz2 | |
x86-64-asm: Add mov[sz]xq opcodes
This adds the zero/sign-extending opcodes with 64bit destinations.
| -rw-r--r-- | i386-tok.h | 3 | ||||
| -rw-r--r-- | tests/asmtest.S | 7 | ||||
| -rw-r--r-- | x86_64-asm.h | 5 |
3 files changed, 14 insertions, 1 deletions
@@ -152,6 +152,9 @@ DEF_ASM(movsbl) DEF_ASM(movswl) #ifdef TCC_TARGET_X86_64 + DEF_ASM(movsbq) + DEF_ASM(movswq) + DEF_ASM(movzwq) DEF_ASM(movslq) #endif diff --git a/tests/asmtest.S b/tests/asmtest.S index 3589f33..e50a5d0 100644 --- a/tests/asmtest.S +++ b/tests/asmtest.S @@ -86,6 +86,13 @@ movl %ebx, %fs movzb 0x1000, %eax movzb 0x1000, %ax +#ifdef __x86_64__ + movzb 0x1000, %rax + movzbq 0x1000, %rbx + movsbq 0x1000, %rdx + movzwq 0x1000, %rdi + movswq 0x1000, %rdx +#endif #ifdef __i386__ pushl %eax diff --git a/x86_64-asm.h b/x86_64-asm.h index f047e81..cea4693 100644 --- a/x86_64-asm.h +++ b/x86_64-asm.h @@ -114,12 +114,15 @@ ALT(DEF_ASM_OP2(movw, 0x0f21, 0, OPC_MODRM | OPC_WLQ, OPT_DB, OPT_REG64)) ALT(DEF_ASM_OP2(movw, 0x0f22, 0, OPC_MODRM | OPC_WLQ, OPT_REG64, OPT_CR)) ALT(DEF_ASM_OP2(movw, 0x0f23, 0, OPC_MODRM | OPC_WLQ, OPT_REG64, OPT_DB)) -ALT(DEF_ASM_OP2(movsbl, 0x0fbe, 0, OPC_MODRM, OPT_REG8 | OPT_EA, OPT_REG32)) ALT(DEF_ASM_OP2(movsbw, 0x0fbe, 0, OPC_MODRM | OPC_D16, OPT_REG8 | OPT_EA, OPT_REG16)) +ALT(DEF_ASM_OP2(movsbl, 0x0fbe, 0, OPC_MODRM, OPT_REG8 | OPT_EA, OPT_REG32)) +ALT(DEF_ASM_OP2(movsbq, 0x0fbe, 0, OPC_MODRM, OPT_REG8 | OPT_EA, OPT_REGW)) ALT(DEF_ASM_OP2(movswl, 0x0fbf, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32)) +ALT(DEF_ASM_OP2(movswq, 0x0fbf, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG)) ALT(DEF_ASM_OP2(movslq, 0x4863, 0, OPC_MODRM, OPT_REG32 | OPT_EA, OPT_REG)) ALT(DEF_ASM_OP2(movzbw, 0x0fb6, 0, OPC_MODRM | OPC_WLQ, OPT_REG8 | OPT_EA, OPT_REGW)) ALT(DEF_ASM_OP2(movzwl, 0x0fb7, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32)) +ALT(DEF_ASM_OP2(movzwq, 0x0fb7, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG)) ALT(DEF_ASM_OP1(pushq, 0x6a, 0, 0, OPT_IM8S)) ALT(DEF_ASM_OP1(push, 0x6a, 0, 0, OPT_IM8S)) |