tinycc/x86_64-asm.h, branch main Tiny C Compiler by Fabrice Bellard Git mirror of the final release by Bellard, discarding all changes after. The repository at https://repo.or.cz/tinycc.git has become untrustworthy. Also the tcc sources have become tainted with AI slop. x86-64-asm: Fix mov im64,rax encoding 2017-02-22T23:16:25+00:00 Michael Matz matz@suse.de 2017-02-22T23:16:25+00:00 3e4c296ebab341bbe95974e39b589ea821f02789 the avoidance of mov im32->reg64 wasn't working when reg64 was rax. While fixing this also fix instructions which had the REX prefix hardcoded in opcode and so didn't support extended registers which would have added another REX prefix. 
the avoidance of mov im32->reg64 wasn't working when reg64 was rax.
While fixing this also fix instructions which had the REX prefix
hardcoded in opcode and so didn't support extended registers which
would have added another REX prefix.
x86-64-asm: Implement cmpxchg16b 2016-12-15T16:47:10+00:00 Michael Matz matz@suse.de 2016-08-08T18:28:21+00:00 9e0af6d2b513ed7ee2f6221bbdf85a8e54e00fc1 






x86-64-asm: Fix ltr/str and push/pop operands
2016-12-15T16:47:10+00:00

Michael Matz
matz@suse.de

2016-08-06T21:19:04+00:00

c0368604e196d53b281cd2aceb140b5facd36ed7

str accepts rm16/r32/r64, and push/pop defaults to 64 when given
memory operands (to 32 on i386).





str accepts rm16/r32/r64, and push/pop defaults to 64 when given
memory operands (to 32 on i386).







x86-asm: Implement prefetchw opcode
2016-12-15T16:47:08+00:00

Michael Matz
matz@suse.de

2016-07-11T20:06:27+00:00

10e4db45dca082b6e936c5540d9f68156b3a8e79












x86-asm: Fix lar opcode operands
2016-12-15T16:47:08+00:00

Michael Matz
matz@suse.de

2016-07-11T19:41:15+00:00

5692716770e9e2e733d0e7ab6ce0bd70cb830aba

lar can accept multiple sizes as well (wlx), like lsl.  When using
autosize it's important to look at the destination operand first;
when it's a register that one determines the size, not the input
operand.





lar can accept multiple sizes as well (wlx), like lsl.  When using
autosize it's important to look at the destination operand first;
when it's a register that one determines the size, not the input
operand.







x86-asm: More opcodes
2016-12-15T16:47:08+00:00

Michael Matz
matz@suse.de

2016-07-11T19:11:13+00:00

6a5ec8cb3cce7399facad79f0cb1513018220b84

Some new opcodes and some aliases: ljmp[wl], prefetch{nta,t0,t1,t2},
bswap[lq], sysretq, swapgs.





Some new opcodes and some aliases: ljmp[wl], prefetch{nta,t0,t1,t2},
bswap[lq], sysretq, swapgs.







x86-asm: Add [sl][ig]dtq opcodes
2016-12-15T16:47:08+00:00

Michael Matz
matz@suse.de

2016-07-11T17:57:39+00:00

d9d029006cc40b22c1555bade4d4048749537c21

GAS has alias lgdtq for lgdt (similar for saves and GDT).  It doesn't
have the same for LDT.





GAS has alias lgdtq for lgdt (similar for saves and GDT).  It doesn't
have the same for LDT.







x86-asm: Implement fxrstorq and fxsaveq
2016-12-15T16:47:08+00:00

Michael Matz
matz@suse.de

2016-07-11T16:53:44+00:00

f6c1eb10e2b1f61210484958b181df20c6b0cad2












x86-asm: Implement clflush opcode
2016-12-15T16:47:08+00:00

Michael Matz
matz@suse.de

2016-07-11T15:25:18+00:00

7e515466246b30f02867fc1f1902dea706ff31af












x86-64-asm: More opcodes
2016-12-15T16:47:07+00:00

Michael Matz
matz@suse.de

2016-06-30T14:14:32+00:00

920474115c3182b19008598b0def86cb8fdf1318

Implement some more opcodes, syscall, sysret, lfence, mfence, sfence.





Implement some more opcodes, syscall, sysret, lfence, mfence, sfence.